[llvm] 183d6af - [llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC
Jon Roelofs via llvm-commits
llvm-commits at lists.llvm.org
Thu May 21 08:29:56 PDT 2020
Author: Jon Roelofs
Date: 2020-05-21T09:29:27-06:00
New Revision: 183d6af081899973f00fc24aeafcfc32de732f02
URL: https://github.com/llvm/llvm-project/commit/183d6af081899973f00fc24aeafcfc32de732f02
DIFF: https://github.com/llvm/llvm-project/commit/183d6af081899973f00fc24aeafcfc32de732f02.diff
LOG: [llvm][test] Add COM: directives before colon-less non-CHECKs in comments. NFC
Differential Revision: https://reviews.llvm.org/D79963
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
llvm/test/CodeGen/AMDGPU/global-constant.ll
llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
llvm/test/CodeGen/AMDGPU/smrd.ll
llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
llvm/test/CodeGen/ARM/build-attributes.ll
llvm/test/CodeGen/ARM/float-helpers.s
llvm/test/CodeGen/ARM/select-imm.ll
llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
llvm/test/CodeGen/Mips/cconv/arguments-float.ll
llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
llvm/test/CodeGen/Mips/cconv/arguments.ll
llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll
llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
llvm/test/CodeGen/Mips/countleading.ll
llvm/test/CodeGen/Mips/divrem.ll
llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
llvm/test/CodeGen/Mips/mips64muldiv.ll
llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
llvm/test/CodeGen/X86/avx-cast.ll
llvm/test/CodeGen/X86/fp-intrinsics.ll
llvm/test/CodeGen/X86/splat-for-size.ll
llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
llvm/test/CodeGen/X86/vec_shift6.ll
llvm/test/CodeGen/X86/vector-compare-combines.ll
llvm/test/CodeGen/X86/vector-narrow-binop.ll
llvm/test/DebugInfo/COFF/vframe-fpo.ll
llvm/test/DebugInfo/X86/debug-info-static-member.ll
llvm/test/FileCheck/dump-input-annotations.txt
llvm/test/FileCheck/var-scope.txt
llvm/test/MC/AsmParser/expr-shr.s
llvm/test/MC/Mips/relocation-n64.s
llvm/test/MC/Mips/relocation.s
llvm/test/MC/RISCV/compressed-relocations.s
llvm/test/MC/RISCV/relocations.s
llvm/test/MC/RISCV/rv32b-aliases-valid.s
llvm/test/MC/RISCV/rv64b-aliases-valid.s
llvm/test/MC/RISCV/rva-aliases-valid.s
llvm/test/MC/RISCV/rvi-aliases-valid.s
llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
llvm/test/Transforms/LoopFusion/cannot_fuse.ll
llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test
llvm/test/tools/llvm-readobj/ELF/section-types.test
llvm/test/tools/llvm-readobj/ELF/symbol-binding.test
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
index d3e806d22ac6..bc09f77cb228 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
@@ -89,7 +89,7 @@ entry:
ret void
}
-; GFX9_10 can use a signed immediate byte offset
+; COM: GFX9_10 can use a signed immediate byte offset
; GCN-LABEL: {{^}}smrd6:
; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -4
; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
index 3fdb2b02ebf2..65fda95c00d8 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
@@ -240,9 +240,9 @@ define amdgpu_kernel void @fp_to_uint_fabs_f32_to_i1(i1 addrspace(1)* %out, floa
}
; FUNC-LABEL: {{^}}fp_to_uint_f32_to_i16:
-; The reason
diff erent instructions are used on SI and VI is because for
-; SI fp_to_uint is legalized by the type legalizer and for VI it is
-; legalized by the dag legalizer and they legalize fp_to_uint
diff erently.
+; COM: The reason
diff erent instructions are used on SI and VI is because for
+; COM: SI fp_to_uint is legalized by the type legalizer and for VI it is
+; COM: legalized by the dag legalizer and they legalize fp_to_uint
diff erently.
; SI: v_cvt_u32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
; VI: v_cvt_i32_f32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
; GCN: buffer_store_short [[VAL]]
diff --git a/llvm/test/CodeGen/AMDGPU/global-constant.ll b/llvm/test/CodeGen/AMDGPU/global-constant.ll
index 479f026b8245..6cfec6869ed1 100644
--- a/llvm/test/CodeGen/AMDGPU/global-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-constant.ll
@@ -11,21 +11,21 @@
; GCN-LABEL: {{^}}private_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
-; PAL OSes use fixup into .text section.
+; COM: PAL OSes use fixup into .text section.
; PAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
-; Non-PAL OSes use relocations.
+; COM: Non-PAL OSes use relocations.
; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 at rel32@lo+4
; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1 at rel32@hi+4
; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
-; PAL OSes use fixup into .text section.
+; COM: PAL OSes use fixup into .text section.
; PAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
; PAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
-; Non-PAL OSes use relocations.
+; COM: Non-PAL OSes use relocations.
; NOPAL: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2 at rel32@lo+4
; NOPAL: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2 at rel32@hi+4
diff --git a/llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir b/llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
index 1f10a047f7d9..ba4e4c6c84c8 100644
--- a/llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
+++ b/llvm/test/CodeGen/AMDGPU/merge-tbuffer.mir
@@ -2,7 +2,7 @@
# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-load-store-opt -o - %s | FileCheck -check-prefix=GFX10 %s
#
-# GFX9 tests
+# COM: GFX9 tests
#
# GFX9-LABEL: name: gfx9_tbuffer_load_x_xyz
@@ -780,7 +780,7 @@ body: |
#
-# GFX10 tests
+# COM: GFX10 tests
#
# GFX10-LABEL: name: gfx10_tbuffer_load_x_xyz
diff --git a/llvm/test/CodeGen/AMDGPU/smrd.ll b/llvm/test/CodeGen/AMDGPU/smrd.ll
index 639ed313522c..3545fd6f025c 100644
--- a/llvm/test/CodeGen/AMDGPU/smrd.ll
+++ b/llvm/test/CodeGen/AMDGPU/smrd.ll
@@ -88,7 +88,7 @@ entry:
ret void
}
-; GFX9_10 can use a signed immediate byte offset
+; COM: GFX9_10 can use a signed immediate byte offset
; GCN-LABEL: {{^}}smrd6:
; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -4
; SICIVI: s_load_dword s{{[0-9]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll b/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
index 1bb427693171..282626451e28 100644
--- a/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
+++ b/llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
@@ -2,7 +2,7 @@
; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s
; XUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s
-; SI hits an assertion at -O0, evergreen hits a not implemented unreachable.
+; COM: SI hits an assertion at -O0, evergreen hits a not implemented unreachable.
; COMMON-LABEL: {{^}}branch_true:
define amdgpu_kernel void @branch_true(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 {
diff --git a/llvm/test/CodeGen/ARM/build-attributes.ll b/llvm/test/CodeGen/ARM/build-attributes.ll
index c08ff35e85fb..011697d8a141 100644
--- a/llvm/test/CodeGen/ARM/build-attributes.ll
+++ b/llvm/test/CodeGen/ARM/build-attributes.ll
@@ -245,17 +245,17 @@
; V6: .eabi_attribute 6, 6
; V6: .eabi_attribute 8, 1
-;; We assume round-to-nearest by default (matches GCC)
+; COM: We assume round-to-nearest by default (matches GCC)
; V6-NOT: .eabi_attribute 27
; V6-NOT: .eabi_attribute 36
; V6-NOT: .eabi_attribute 42
; V6-NOT: .eabi_attribute 44
; V6-NOT: .eabi_attribute 68
; V6-NOT: .eabi_attribute 19
-;; The default choice made by llc is for a V6 CPU without an FPU.
-;; This is not an interesting detail, but for such CPUs, the default intention is to use
-;; software floating-point support. The choice is not important for targets without
-;; FPU support!
+; COM: The default choice made by llc is for a V6 CPU without an FPU.
+; COM: This is not an interesting detail, but for such CPUs, the default intention is to use
+; COM: software floating-point support. The choice is not important for targets without
+; COM: FPU support!
; V6: .eabi_attribute 20, 1
; V6: .eabi_attribute 21, 1
; V6-NOT: .eabi_attribute 22
@@ -266,16 +266,16 @@
; V6: .eabi_attribute 38, 1
; V6-FAST-NOT: .eabi_attribute 19
-;; Despite the V6 CPU having no FPU by default, we chose to flush to
-;; positive zero here. There's no hardware support doing this, but the
-;; fast maths software library might.
+; COM: Despite the V6 CPU having no FPU by default, we chose to flush to
+; COM: positive zero here. There's no hardware support doing this, but the
+; COM: fast maths software library might.
; V6-FAST-NOT: .eabi_attribute 20
; V6-FAST-NOT: .eabi_attribute 21
; V6-FAST-NOT: .eabi_attribute 22
; V6-FAST: .eabi_attribute 23, 1
-;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
-;; V6-M, however we don't model the OS extension so this is fine.
+; COM: We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for
+; COM: V6-M, however we don't model the OS extension so this is fine.
; V6M: .eabi_attribute 6, 12
; V6M: .eabi_attribute 7, 77
; V6M: .eabi_attribute 8, 0
@@ -286,10 +286,10 @@
; V6M-NOT: .eabi_attribute 44
; V6M-NOT: .eabi_attribute 68
; V6M-NOT: .eabi_attribute 19
-;; The default choice made by llc is for a V6M CPU without an FPU.
-;; This is not an interesting detail, but for such CPUs, the default intention is to use
-;; software floating-point support. The choice is not important for targets without
-;; FPU support!
+; COM: The default choice made by llc is for a V6M CPU without an FPU.
+; COM: This is not an interesting detail, but for such CPUs, the default intention is to use
+; COM: software floating-point support. The choice is not important for targets without
+; COM: FPU support!
; V6M: .eabi_attribute 20, 1
; V6M: .eabi_attribute 21, 1
; V6M-NOT: .eabi_attribute 22
@@ -300,9 +300,9 @@
; V6M: .eabi_attribute 38, 1
; V6M-FAST-NOT: .eabi_attribute 19
-;; Despite the V6M CPU having no FPU by default, we chose to flush to
-;; positive zero here. There's no hardware support doing this, but the
-;; fast maths software library might.
+; COM: Despite the V6M CPU having no FPU by default, we chose to flush to
+; COM: positive zero here. There's no hardware support doing this, but the
+; COM: fast maths software library might.
; V6M-FAST-NOT: .eabi_attribute 20
; V6M-FAST-NOT: .eabi_attribute 21
; V6M-FAST-NOT: .eabi_attribute 22
@@ -319,7 +319,7 @@
; ARM1156T2F-S-NOT: .eabi_attribute 44
; ARM1156T2F-S-NOT: .eabi_attribute 68
; ARM1156T2F-S-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; ARM1156T2F-S: .eabi_attribute 20, 1
; ARM1156T2F-S: .eabi_attribute 21, 1
; ARM1156T2F-S-NOT: .eabi_attribute 22
@@ -330,9 +330,9 @@
; ARM1156T2F-S: .eabi_attribute 38, 1
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 19
-;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
-;; valid for this core, it's an implementation defined question as to which of 0 and 2 you
-;; select. LLVM historically picks 0.
+; COM: V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
+; COM: valid for this core, it's an implementation defined question as to which of 0 and 2 you
+; COM: select. LLVM historically picks 0.
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 21
; ARM1156T2F-S-FAST-NOT: .eabi_attribute 22
@@ -348,10 +348,10 @@
; V7M-NOT: .eabi_attribute 44
; V7M-NOT: .eabi_attribute 68
; V7M-NOT: .eabi_attribute 19
-;; The default choice made by llc is for a V7M CPU without an FPU.
-;; This is not an interesting detail, but for such CPUs, the default intention is to use
-;; software floating-point support. The choice is not important for targets without
-;; FPU support!
+; COM: The default choice made by llc is for a V7M CPU without an FPU.
+; COM: This is not an interesting detail, but for such CPUs, the default intention is to use
+; COM: software floating-point support. The choice is not important for targets without
+; COM: FPU support!
; V7M: .eabi_attribute 20, 1
; V7M: .eabi_attribute 21, 1
; V7M-NOT: .eabi_attribute 22
@@ -362,9 +362,9 @@
; V7M: .eabi_attribute 38, 1
; V7M-FAST-NOT: .eabi_attribute 19
-;; Despite the V7M CPU having no FPU by default, we chose to flush
-;; preserving sign. This matches what the hardware would do in the
-;; architecture revision were to exist on the current target.
+; COM: Despite the V7M CPU having no FPU by default, we chose to flush
+; COM: preserving sign. This matches what the hardware would do in the
+; COM: architecture revision were to exist on the current target.
; V7M-FAST: .eabi_attribute 20, 2
; V7M-FAST-NOT: .eabi_attribute 21
; V7M-FAST-NOT: .eabi_attribute 22
@@ -378,7 +378,7 @@
; V7-NOT: .eabi_attribute 44
; V7-NOT: .eabi_attribute 68
; V7-NOT: .eabi_attribute 19
-;; In safe-maths mode we default to an IEEE 754 compliant choice.
+; COM: In safe-maths mode we default to an IEEE 754 compliant choice.
; V7: .eabi_attribute 20, 1
; V7: .eabi_attribute 21, 1
; V7-NOT: .eabi_attribute 22
@@ -389,8 +389,8 @@
; V7: .eabi_attribute 38, 1
; V7-FAST-NOT: .eabi_attribute 19
-;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
-;; denormals to zero preserving the sign.
+; COM: The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
+; COM: denormals to zero preserving the sign.
; V7-FAST: .eabi_attribute 20, 2
; V7-FAST-NOT: .eabi_attribute 21
; V7-FAST-NOT: .eabi_attribute 22
@@ -423,7 +423,7 @@
; V8: .eabi_attribute 23, 3
; V8-FAST-NOT: .eabi_attribute 19
-;; The default does have an FPU, and for V8-A, it flushes preserving sign.
+; COM: The default does have an FPU, and for V8-A, it flushes preserving sign.
; V8-FAST: .eabi_attribute 20, 2
; V8-FAST-NOT: .eabi_attribute 21
; V8-FAST-NOT: .eabi_attribute 22
@@ -536,17 +536,17 @@
; CORTEX-A7-FPUV4: .eabi_attribute 68, 3
; Tag_ABI_FP_denormal
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A7-CHECK: .eabi_attribute 20, 1
-;; The A7 has VFPv3 support by default, so flush preserving sign.
+; COM: The A7 has VFPv3 support by default, so flush preserving sign.
; CORTEX-A7-CHECK-FAST: .eabi_attribute 20, 2
; CORTEX-A7-NOFPU: .eabi_attribute 20, 1
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; CORTEX-A7-NOFPU-FAST: .eabi_attribute 20, 2
; CORTEX-A7-FPUV4: .eabi_attribute 20, 1
-;; The VFPv4 FPU flushes preserving sign.
+; COM: The VFPv4 FPU flushes preserving sign.
; CORTEX-A7-FPUV4-FAST: .eabi_attribute 20, 2
; Tag_ABI_FP_exceptions
@@ -589,7 +589,7 @@
; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 44
; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1
; CORTEX-A5-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A5-DEFAULT: .eabi_attribute 20, 1
; CORTEX-A5-DEFAULT: .eabi_attribute 21, 1
; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 22
@@ -598,8 +598,8 @@
; CORTEX-A5-DEFAULT: .eabi_attribute 25, 1
; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 19
-;; The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math
-;; is given.
+; COM: The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math
+; COM: is given.
; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 20, 2
; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21
; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 22
@@ -613,7 +613,7 @@
; CORTEX-A5-NONEON: .fpu vfpv4-d16
; CORTEX-A5-NONEON: .eabi_attribute 42, 1
; CORTEX-A5-NONEON: .eabi_attribute 68, 1
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A5-NONEON: .eabi_attribute 20, 1
; CORTEX-A5-NONEON: .eabi_attribute 21, 1
; CORTEX-A5-NONEON-NOT: .eabi_attribute 22
@@ -622,8 +622,8 @@
; CORTEX-A5-NONEON: .eabi_attribute 25, 1
; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 19
-;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
-;; is given.
+; COM: The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
+; COM: is given.
; CORTEX-A5-NONEON-FAST: .eabi_attribute 20, 2
; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 21
; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 22
@@ -638,7 +638,7 @@
; CORTEX-A5-NOFPU: .eabi_attribute 42, 1
; CORTEX-A5-NOFPU: .eabi_attribute 68, 1
; CORTEX-A5-NOFPU-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A5-NOFPU: .eabi_attribute 20, 1
; CORTEX-A5-NOFPU: .eabi_attribute 21, 1
; CORTEX-A5-NOFPU-NOT: .eabi_attribute 22
@@ -647,9 +647,9 @@
; CORTEX-A5-NOFPU: .eabi_attribute 25, 1
; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 19
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; CORTEX-A5-NOFPU-FAST: .eabi_attribute 20, 2
; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 21
; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 22
@@ -667,7 +667,7 @@
; CORTEX-A8-SOFT-NOT: .eabi_attribute 44
; CORTEX-A8-SOFT: .eabi_attribute 68, 1
; CORTEX-A8-SOFT-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A8-SOFT: .eabi_attribute 20, 1
; CORTEX-A8-SOFT: .eabi_attribute 21, 1
; CORTEX-A8-SOFT-NOT: .eabi_attribute 22
@@ -689,7 +689,7 @@
; CORTEX-A9-SOFT-NOT: .eabi_attribute 44
; CORTEX-A9-SOFT: .eabi_attribute 68, 1
; CORTEX-A9-SOFT-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A9-SOFT: .eabi_attribute 20, 1
; CORTEX-A9-SOFT: .eabi_attribute 21, 1
; CORTEX-A9-SOFT-NOT: .eabi_attribute 22
@@ -701,8 +701,8 @@
; CORTEX-A8-SOFT-FAST-NOT: .eabi_attribute 19
; CORTEX-A9-SOFT-FAST-NOT: .eabi_attribute 19
-;; The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-A8-SOFT-FAST: .eabi_attribute 20, 2
; CORTEX-A9-SOFT-FAST: .eabi_attribute 20, 2
; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21
@@ -720,7 +720,7 @@
; CORTEX-A8-HARD-NOT: .eabi_attribute 42, 1
; CORTEX-A8-HARD: .eabi_attribute 68, 1
; CORTEX-A8-HARD-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A8-HARD: .eabi_attribute 20, 1
; CORTEX-A8-HARD: .eabi_attribute 21, 1
; CORTEX-A8-HARD-NOT: .eabi_attribute 22
@@ -743,7 +743,7 @@
; CORTEX-A9-HARD: .eabi_attribute 42, 1
; CORTEX-A9-HARD: .eabi_attribute 68, 1
; CORTEX-A9-HARD-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A9-HARD: .eabi_attribute 20, 1
; CORTEX-A9-HARD: .eabi_attribute 21, 1
; CORTEX-A9-HARD-NOT: .eabi_attribute 22
@@ -754,16 +754,16 @@
; CORTEX-A9-HARD: .eabi_attribute 38, 1
; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 19
-;; The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-A8-HARD-FAST: .eabi_attribute 20, 2
; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 21
; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 22
; CORTEX-A8-HARD-FAST: .eabi_attribute 23, 1
; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 19
-;; The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-A9-HARD-FAST: .eabi_attribute 20, 2
; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 21
; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 22
@@ -779,7 +779,7 @@
; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2
; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A12-DEFAULT: .eabi_attribute 20, 1
; CORTEX-A12-DEFAULT: .eabi_attribute 21, 1
; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 22
@@ -788,8 +788,8 @@
; CORTEX-A12-DEFAULT: .eabi_attribute 25, 1
; CORTEX-A12-DEFAULT-FAST-NOT: .eabi_attribute 19
-;; The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-A12-DEFAULT-FAST: .eabi_attribute 20, 2
; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 21
; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 22
@@ -805,7 +805,7 @@
; CORTEX-A12-NOFPU: .eabi_attribute 44, 2
; CORTEX-A12-NOFPU: .eabi_attribute 68, 3
; CORTEX-A12-NOFPU-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A12-NOFPU: .eabi_attribute 20, 1
; CORTEX-A12-NOFPU: .eabi_attribute 21, 1
; CORTEX-A12-NOFPU-NOT: .eabi_attribute 22
@@ -814,9 +814,9 @@
; CORTEX-A12-NOFPU: .eabi_attribute 25, 1
; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 19
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; CORTEX-A12-NOFPU-FAST: .eabi_attribute 20, 2
; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 21
; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 22
@@ -834,7 +834,7 @@
; CORTEX-A15: .eabi_attribute 44, 2
; CORTEX-A15: .eabi_attribute 68, 3
; CORTEX-A15-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A15: .eabi_attribute 20, 1
; CORTEX-A15: .eabi_attribute 21, 1
; CORTEX-A15-NOT: .eabi_attribute 22
@@ -845,8 +845,8 @@
; CORTEX-A15: .eabi_attribute 38, 1
; CORTEX-A15-FAST-NOT: .eabi_attribute 19
-;; The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-A15-FAST: .eabi_attribute 20, 2
; CORTEX-A15-FAST-NOT: .eabi_attribute 21
; CORTEX-A15-FAST-NOT: .eabi_attribute 22
@@ -862,7 +862,7 @@
; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1
; CORTEX-A17-DEFAULT: .eabi_attribute 21, 1
; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 22
@@ -871,8 +871,8 @@
; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1
; CORTEX-A17-FAST-NOT: .eabi_attribute 19
-;; The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-A17-FAST: .eabi_attribute 20, 2
; CORTEX-A17-FAST-NOT: .eabi_attribute 21
; CORTEX-A17-FAST-NOT: .eabi_attribute 22
@@ -888,7 +888,7 @@
; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A17-NOFPU: .eabi_attribute 20, 1
; CORTEX-A17-NOFPU: .eabi_attribute 21, 1
; CORTEX-A17-NOFPU-NOT: .eabi_attribute 22
@@ -897,9 +897,9 @@
; CORTEX-A17-NOFPU: .eabi_attribute 25, 1
; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; CORTEX-A17-NOFPU-FAST: .eabi_attribute 20, 2
; CORTEX-A17-NOFPU-FAST-NOT: .eabi_attribute 21
; CORTEX-A17-NOFPU-FAST-NOT: .eabi_attribute 22
@@ -923,7 +923,7 @@
; CORTEX-M0-NOT: .eabi_attribute 44
; CORTEX-M0-NOT: .eabi_attribute 68
; CORTEX-M0-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M0: .eabi_attribute 20, 1
; CORTEX-M0: .eabi_attribute 21, 1
; CORTEX-M0-NOT: .eabi_attribute 22
@@ -934,11 +934,11 @@
; CORTEX-M0: .eabi_attribute 38, 1
; CORTEX-M0-FAST-NOT: .eabi_attribute 19
-;; Despite the M0 CPU having no FPU in this scenario, we chose to
-;; flush to positive zero here. There's no hardware support doing
-;; this, but the fast maths software library might and such behaviour
-;; would match hardware support on this architecture revision if it
-;; existed.
+; COM: Despite the M0 CPU having no FPU in this scenario, we chose to
+; COM: flush to positive zero here. There's no hardware support doing
+; COM: this, but the fast maths software library might and such behaviour
+; COM: would match hardware support on this architecture revision if it
+; COM: existed.
; CORTEX-M0-FAST-NOT: .eabi_attribute 20
; CORTEX-M0-FAST-NOT: .eabi_attribute 21
; CORTEX-M0-FAST-NOT: .eabi_attribute 22
@@ -955,7 +955,7 @@
; CORTEX-M0PLUS-NOT: .eabi_attribute 44
; CORTEX-M0PLUS-NOT: .eabi_attribute 68
; CORTEX-M0PLUS-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M0PLUS: .eabi_attribute 20, 1
; CORTEX-M0PLUS: .eabi_attribute 21, 1
; CORTEX-M0PLUS-NOT: .eabi_attribute 22
@@ -966,11 +966,11 @@
; CORTEX-M0PLUS: .eabi_attribute 38, 1
; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 19
-;; Despite the M0+ CPU having no FPU in this scenario, we chose to
-;; flush to positive zero here. There's no hardware support doing
-;; this, but the fast maths software library might and such behaviour
-;; would match hardware support on this architecture revision if it
-;; existed.
+; COM: Despite the M0+ CPU having no FPU in this scenario, we chose to
+; COM: flush to positive zero here. There's no hardware support doing
+; COM: this, but the fast maths software library might and such behaviour
+; COM: would match hardware support on this architecture revision if it
+; COM: existed.
; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 20
; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 21
; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 22
@@ -987,7 +987,7 @@
; CORTEX-M1-NOT: .eabi_attribute 44
; CORTEX-M1-NOT: .eabi_attribute 68
; CORTEX-M1-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M1: .eabi_attribute 20, 1
; CORTEX-M1: .eabi_attribute 21, 1
; CORTEX-M1-NOT: .eabi_attribute 22
@@ -998,11 +998,11 @@
; CORTEX-M1: .eabi_attribute 38, 1
; CORTEX-M1-FAST-NOT: .eabi_attribute 19
-;; Despite the M1 CPU having no FPU in this scenario, we chose to
-;; flush to positive zero here. There's no hardware support doing
-;; this, but the fast maths software library might and such behaviour
-;; would match hardware support on this architecture revision if it
-;; existed.
+; COM: Despite the M1 CPU having no FPU in this scenario, we chose to
+; COM: flush to positive zero here. There's no hardware support doing
+; COM: this, but the fast maths software library might and such behaviour
+; COM: would match hardware support on this architecture revision if it
+; COM: existed.
; CORTEX-M1-FAST-NOT: .eabi_attribute 20
; CORTEX-M1-FAST-NOT: .eabi_attribute 21
; CORTEX-M1-FAST-NOT: .eabi_attribute 22
@@ -1018,7 +1018,7 @@
; SC000-NOT: .eabi_attribute 44
; SC000-NOT: .eabi_attribute 68
; SC000-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; SC000: .eabi_attribute 20, 1
; SC000: .eabi_attribute 21, 1
; SC000-NOT: .eabi_attribute 22
@@ -1029,11 +1029,11 @@
; SC000: .eabi_attribute 38, 1
; SC000-FAST-NOT: .eabi_attribute 19
-;; Despite the SC000 CPU having no FPU in this scenario, we chose to
-;; flush to positive zero here. There's no hardware support doing
-;; this, but the fast maths software library might and such behaviour
-;; would match hardware support on this architecture revision if it
-;; existed.
+; COM: Despite the SC000 CPU having no FPU in this scenario, we chose to
+; COM: flush to positive zero here. There's no hardware support doing
+; COM: this, but the fast maths software library might and such behaviour
+; COM: would match hardware support on this architecture revision if it
+; COM: existed.
; SC000-FAST-NOT: .eabi_attribute 20
; SC000-FAST-NOT: .eabi_attribute 21
; SC000-FAST-NOT: .eabi_attribute 22
@@ -1050,7 +1050,7 @@
; CORTEX-M3-NOT: .eabi_attribute 44
; CORTEX-M3-NOT: .eabi_attribute 68
; CORTEX-M3-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M3: .eabi_attribute 20, 1
; CORTEX-M3: .eabi_attribute 21, 1
; CORTEX-M3-NOT: .eabi_attribute 22
@@ -1061,9 +1061,9 @@
; CORTEX-M3: .eabi_attribute 38, 1
; CORTEX-M3-FAST-NOT: .eabi_attribute 19
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; CORTEX-M3-FAST: .eabi_attribute 20, 2
; CORTEX-M3-FAST-NOT: .eabi_attribute 21
; CORTEX-M3-FAST-NOT: .eabi_attribute 22
@@ -1080,7 +1080,7 @@
; SC300-NOT: .eabi_attribute 44
; SC300-NOT: .eabi_attribute 68
; SC300-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; SC300: .eabi_attribute 20, 1
; SC300: .eabi_attribute 21, 1
; SC300-NOT: .eabi_attribute 22
@@ -1091,9 +1091,9 @@
; SC300: .eabi_attribute 38, 1
; SC300-FAST-NOT: .eabi_attribute 19
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; SC300-FAST: .eabi_attribute 20, 2
; SC300-FAST-NOT: .eabi_attribute 21
; SC300-FAST-NOT: .eabi_attribute 22
@@ -1111,7 +1111,7 @@
; CORTEX-M4-SOFT-NOT: .eabi_attribute 44
; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
; CORTEX-M4-SOFT-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M4-SOFT: .eabi_attribute 20, 1
; CORTEX-M4-SOFT: .eabi_attribute 21, 1
; CORTEX-M4-SOFT-NOT: .eabi_attribute 22
@@ -1122,8 +1122,8 @@
; CORTEX-M4-SOFT: .eabi_attribute 38, 1
; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 19
-;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-M4-SOFT-FAST: .eabi_attribute 20, 2
; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 21
; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 22
@@ -1141,7 +1141,7 @@
; CORTEX-M4-HARD-NOT: .eabi_attribute 44
; CORTEX-M4-HARD-NOT: .eabi_attribute 68
; CORTEX-M4-HARD-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M4-HARD: .eabi_attribute 20, 1
; CORTEX-M4-HARD: .eabi_attribute 21, 1
; CORTEX-M4-HARD-NOT: .eabi_attribute 22
@@ -1152,8 +1152,8 @@
; CORTEX-M4-HARD: .eabi_attribute 38, 1
; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 19
-;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
-;; -ffast-math is specified.
+; COM: The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when
+; COM: -ffast-math is specified.
; CORTEX-M4-HARD-FAST: .eabi_attribute 20, 2
; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 21
; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 22
@@ -1174,7 +1174,7 @@
; CORTEX-M7-NOT: .eabi_attribute 44
; CORTEX-M7: .eabi_attribute 17, 1
; CORTEX-M7-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M7: .eabi_attribute 20, 1
; CORTEX-M7: .eabi_attribute 21, 1
; CORTEX-M7-NOT: .eabi_attribute 22
@@ -1185,11 +1185,11 @@
; CORTEX-M7: .eabi_attribute 14, 0
; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 19
-;; The M7 has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The M7 has the ARMv8 FP unit, which always flushes preserving sign.
; CORTEX-M7-FAST: .eabi_attribute 20, 2
-;; Despite there being no FPU, we chose to flush to zero preserving
-;; sign. This matches what the hardware would do for this architecture
-;; revision.
+; COM: Despite there being no FPU, we chose to flush to zero preserving
+; COM: sign. This matches what the hardware would do for this architecture
+; COM: revision.
; CORTEX-M7-NOFPU-FAST: .eabi_attribute 20, 2
; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 21
; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 22
@@ -1206,7 +1206,7 @@
; CORTEX-R4-NOT: .eabi_attribute 44
; CORTEX-R4-NOT: .eabi_attribute 68
; CORTEX-R4-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-R4: .eabi_attribute 20, 1
; CORTEX-R4: .eabi_attribute 21, 1
; CORTEX-R4-NOT: .eabi_attribute 22
@@ -1228,7 +1228,7 @@
; CORTEX-R4F-NOT: .eabi_attribute 44
; CORTEX-R4F-NOT: .eabi_attribute 68
; CORTEX-R4F-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-R4F: .eabi_attribute 20, 1
; CORTEX-R4F: .eabi_attribute 21, 1
; CORTEX-R4F-NOT: .eabi_attribute 22
@@ -1250,7 +1250,7 @@
; CORTEX-R5-NOT: .eabi_attribute 42
; CORTEX-R5-NOT: .eabi_attribute 68
; CORTEX-R5-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-R5: .eabi_attribute 20, 1
; CORTEX-R5: .eabi_attribute 21, 1
; CORTEX-R5-NOT: .eabi_attribute 22
@@ -1261,7 +1261,7 @@
; CORTEX-R5: .eabi_attribute 38, 1
; CORTEX-R5-FAST-NOT: .eabi_attribute 19
-;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
+; COM: The R5 has the VFPv3 FP unit, which always flushes preserving sign.
; CORTEX-R5-FAST: .eabi_attribute 20, 2
; CORTEX-R5-FAST-NOT: .eabi_attribute 21
; CORTEX-R5-FAST-NOT: .eabi_attribute 22
@@ -1278,7 +1278,7 @@
; CORTEX-R7: .eabi_attribute 44, 2
; CORTEX-R7-NOT: .eabi_attribute 68
; CORTEX-R7-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-R7: .eabi_attribute 20, 1
; CORTEX-R7: .eabi_attribute 21, 1
; CORTEX-R7-NOT: .eabi_attribute 22
@@ -1289,7 +1289,7 @@
; CORTEX-R7: .eabi_attribute 38, 1
; CORTEX-R7-FAST-NOT: .eabi_attribute 19
-;; The R7 has the VFPv3 FP unit, which always flushes preserving sign.
+; COM: The R7 has the VFPv3 FP unit, which always flushes preserving sign.
; CORTEX-R7-FAST: .eabi_attribute 20, 2
; CORTEX-R7-FAST-NOT: .eabi_attribute 21
; CORTEX-R7-FAST-NOT: .eabi_attribute 22
@@ -1306,7 +1306,7 @@
; CORTEX-R8: .eabi_attribute 44, 2
; CORTEX-R8-NOT: .eabi_attribute 68
; CORTEX-R8-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-R8: .eabi_attribute 20, 1
; CORTEX-R8: .eabi_attribute 21, 1
; CORTEX-R8-NOT: .eabi_attribute 22
@@ -1317,7 +1317,7 @@
; CORTEX-R8: .eabi_attribute 38, 1
; CORTEX-R8-FAST-NOT: .eabi_attribute 19
-;; The R8 has the VFPv3 FP unit, which always flushes preserving sign.
+; COM: The R8 has the VFPv3 FP unit, which always flushes preserving sign.
; CORTEX-R8-FAST: .eabi_attribute 20, 2
; CORTEX-R8-FAST-NOT: .eabi_attribute 21
; CORTEX-R8-FAST-NOT: .eabi_attribute 22
@@ -1336,7 +1336,7 @@
; CORTEX-A32-NOT: .eabi_attribute 44
; CORTEX-A32: .eabi_attribute 68, 3
; CORTEX-A32-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A32: .eabi_attribute 20, 1
; CORTEX-A32: .eabi_attribute 21, 1
; CORTEX-A32-NOT: .eabi_attribute 22
@@ -1347,7 +1347,7 @@
; CORTEX-A32: .eabi_attribute 38, 1
; CORTEX-A32-FAST-NOT: .eabi_attribute 19
-;; The A32 has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The A32 has the ARMv8 FP unit, which always flushes preserving sign.
; CORTEX-A32-FAST: .eabi_attribute 20, 2
; CORTEX-A32-FAST-NOT: .eabi_attribute 21
; CORTEX-A32-FAST-NOT: .eabi_attribute 22
@@ -1362,7 +1362,7 @@
; CORTEX-M23: .eabi_attribute 34, 0
; CORTEX-M23-NOT: .eabi_attribute 44
; CORTEX-M23: .eabi_attribute 17, 1
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M23-NOT: .eabi_attribute 19
; CORTEX-M23: .eabi_attribute 20, 1
; CORTEX-M23: .eabi_attribute 21, 1
@@ -1385,7 +1385,7 @@
; CORTEX-M33: .eabi_attribute 46, 1
; CORTEX-M33: .eabi_attribute 34, 1
; CORTEX-M33: .eabi_attribute 17, 1
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-M23-NOT: .eabi_attribute 19
; CORTEX-M33: .eabi_attribute 20, 1
; CORTEX-M33: .eabi_attribute 21, 1
@@ -1436,7 +1436,7 @@
; CORTEX-A35-NOT: .eabi_attribute 44
; CORTEX-A35: .eabi_attribute 68, 3
; CORTEX-A35-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A35: .eabi_attribute 20, 1
; CORTEX-A35: .eabi_attribute 21, 1
; CORTEX-A35-NOT: .eabi_attribute 22
@@ -1447,7 +1447,7 @@
; CORTEX-A35: .eabi_attribute 38, 1
; CORTEX-A35-FAST-NOT: .eabi_attribute 19
-;; The A35 has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The A35 has the ARMv8 FP unit, which always flushes preserving sign.
; CORTEX-A35-FAST: .eabi_attribute 20, 2
; CORTEX-A35-FAST-NOT: .eabi_attribute 21
; CORTEX-A35-FAST-NOT: .eabi_attribute 22
@@ -1466,7 +1466,7 @@
; CORTEX-A53-NOT: .eabi_attribute 44
; CORTEX-A53: .eabi_attribute 68, 3
; CORTEX-A53-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A53: .eabi_attribute 20, 1
; CORTEX-A53: .eabi_attribute 21, 1
; CORTEX-A53-NOT: .eabi_attribute 22
@@ -1477,7 +1477,7 @@
; CORTEX-A53: .eabi_attribute 38, 1
; CORTEX-A53-FAST-NOT: .eabi_attribute 19
-;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The A53 has the ARMv8 FP unit, which always flushes preserving sign.
; CORTEX-A53-FAST: .eabi_attribute 20, 2
; CORTEX-A53-FAST-NOT: .eabi_attribute 21
; CORTEX-A53-FAST-NOT: .eabi_attribute 22
@@ -1496,7 +1496,7 @@
; CORTEX-A57-NOT: .eabi_attribute 44
; CORTEX-A57: .eabi_attribute 68, 3
; CORTEX-A57-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A57: .eabi_attribute 20, 1
; CORTEX-A57: .eabi_attribute 21, 1
; CORTEX-A57-NOT: .eabi_attribute 22
@@ -1507,7 +1507,7 @@
; CORTEX-A57: .eabi_attribute 38, 1
; CORTEX-A57-FAST-NOT: .eabi_attribute 19
-;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The A57 has the ARMv8 FP unit, which always flushes preserving sign.
; CORTEX-A57-FAST: .eabi_attribute 20, 2
; CORTEX-A57-FAST-NOT: .eabi_attribute 21
; CORTEX-A57-FAST-NOT: .eabi_attribute 22
@@ -1526,7 +1526,7 @@
; CORTEX-A72-NOT: .eabi_attribute 44
; CORTEX-A72: .eabi_attribute 68, 3
; CORTEX-A72-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A72: .eabi_attribute 20, 1
; CORTEX-A72: .eabi_attribute 21, 1
; CORTEX-A72-NOT: .eabi_attribute 22
@@ -1537,7 +1537,7 @@
; CORTEX-A72: .eabi_attribute 38, 1
; CORTEX-A72-FAST-NOT: .eabi_attribute 19
-;; The A72 has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The A72 has the ARMv8 FP unit, which always flushes preserving sign.
; CORTEX-A72-FAST: .eabi_attribute 20, 2
; CORTEX-A72-FAST-NOT: .eabi_attribute 21
; CORTEX-A72-FAST-NOT: .eabi_attribute 22
@@ -1556,7 +1556,7 @@
; CORTEX-A73-NOT: .eabi_attribute 44
; CORTEX-A73: .eabi_attribute 68, 3
; CORTEX-A73-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; CORTEX-A73: .eabi_attribute 20, 1
; CORTEX-A73: .eabi_attribute 21, 1
; CORTEX-A73-NOT: .eabi_attribute 22
@@ -1568,7 +1568,7 @@
; CORTEX-A73: .eabi_attribute 14, 0
; EXYNOS-FAST-NOT: .eabi_attribute 19
-;; The Exynos processors have the ARMv8 FP unit, which always flushes preserving sign.
+; COM: The Exynos processors have the ARMv8 FP unit, which always flushes preserving sign.
; EXYNOS-FAST: .eabi_attribute 20, 2
; EXYNOS-FAST-NOT: .eabi_attribute 21
; EXYNOS-FAST-NOT: .eabi_attribute 22
@@ -1587,7 +1587,7 @@
; EXYNOS-M3-NOT: .eabi_attribute 44
; EXYNOS-M3: .eabi_attribute 68, 3
; EXYNOS-M3-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; EXYNOS-M3: .eabi_attribute 20, 1
; EXYNOS-M3: .eabi_attribute 21, 1
; EXYNOS-M3-NOT: .eabi_attribute 22
@@ -1610,7 +1610,7 @@
; EXYNOS-M4-NOT: .eabi_attribute 44
; EXYNOS-M4: .eabi_attribute 68, 3
; EXYNOS-M4-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; EXYNOS-M4: .eabi_attribute 20, 1
; EXYNOS-M4: .eabi_attribute 21, 1
; EXYNOS-M4-NOT: .eabi_attribute 22
@@ -1633,7 +1633,7 @@
; EXYNOS-M5-NOT: .eabi_attribute 44
; EXYNOS-M5: .eabi_attribute 68, 3
; EXYNOS-M5-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; EXYNOS-M5: .eabi_attribute 20, 1
; EXYNOS-M5: .eabi_attribute 21, 1
; EXYNOS-M5-NOT: .eabi_attribute 22
@@ -1661,7 +1661,7 @@
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 44
; GENERIC-ARMV8_1-A: .eabi_attribute 68, 3
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 19
-;; We default to IEEE 754 compliance
+; COM: We default to IEEE 754 compliance
; GENERIC-ARMV8_1-A: .eabi_attribute 20, 1
; GENERIC-ARMV8_1-A: .eabi_attribute 21, 1
; GENERIC-ARMV8_1-A-NOT: .eabi_attribute 22
@@ -1672,7 +1672,7 @@
; GENERIC-ARMV8_1-A: .eabi_attribute 38, 1
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 19
-;; GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
+; COM: GENERIC-ARMV8_1-A has the ARMv8 FP unit, which always flushes preserving sign.
; GENERIC-ARMV8_1-A-FAST: .eabi_attribute 20, 2
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 21
; GENERIC-ARMV8_1-A-FAST-NOT: .eabi_attribute 22
diff --git a/llvm/test/CodeGen/ARM/float-helpers.s b/llvm/test/CodeGen/ARM/float-helpers.s
index 1225b4c999f1..1e3bfed8d161 100644
--- a/llvm/test/CodeGen/ARM/float-helpers.s
+++ b/llvm/test/CodeGen/ARM/float-helpers.s
@@ -12,24 +12,24 @@
; floating-point helper functions to always use the base AAPCS (soft-float)
; calling convention.
-; In this test we cover the following configurations:
-; CHECK-SOFT -mfloat-abi=soft
-; * expect no use of floating point instructions
-; * expect to use __aeabi_ helper function in each function
-; CHECK-SOFTFP -mfloat-abi=softfp
-; * all functions use base AAPCS
-; * floating point instructions permitted, so __aeabi_ helpers only
-; expected when there is no available instruction.
-; CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions)
-; * all non Runtime ABI helper functions use AAPCS VFP
-; * floating point instructions permitted, so __aeabi_ helpers only
-; expected when there is no available instruction.
-; CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions)
-; CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single
-; precision only FPU)
-; * as CHECK-HARDFP-SP, but we split up the double precision helper
-; functions so we can test a single precision only FPU, which has to use
-; helper function for all double precision operations.
+; COM: In this test we cover the following configurations:
+; COM: CHECK-SOFT -mfloat-abi=soft
+; COM: * expect no use of floating point instructions
+; COM: * expect to use __aeabi_ helper function in each function
+; COM: CHECK-SOFTFP -mfloat-abi=softfp
+; COM: * all functions use base AAPCS
+; COM: * floating point instructions permitted, so __aeabi_ helpers only
+; COM: expected when there is no available instruction.
+; COM: CHECK-HARDFP-SP -mfloat-abi=hardfp (single precision instructions)
+; COM: * all non Runtime ABI helper functions use AAPCS VFP
+; COM: * floating point instructions permitted, so __aeabi_ helpers only
+; COM: expected when there is no available instruction.
+; COM: CHECK-HARDFP-DP -mfloat-abi=hardfp (double precision instructions)
+; COM: CHECK-HARDFP-SPONLY -mfloat-abi=hardfp (double precision but single
+; COM: precision only FPU)
+; COM: * as CHECK-HARDFP-SP, but we split up the double precision helper
+; COM: functions so we can test a single precision only FPU, which has to use
+; COM: helper function for all double precision operations.
; In all cases we must use base AAPCS when calling a helper function from
; section 4.1.2.
diff --git a/llvm/test/CodeGen/ARM/select-imm.ll b/llvm/test/CodeGen/ARM/select-imm.ll
index 628bae6e1dc9..39517de6792f 100644
--- a/llvm/test/CodeGen/ARM/select-imm.ll
+++ b/llvm/test/CodeGen/ARM/select-imm.ll
@@ -181,7 +181,7 @@ entry:
define void @t8(i32 %a) {
entry:
-; ARM scheduler emits icmp/zext before both calls, so isn't relevant
+; COM: ARM scheduler emits icmp/zext before both calls, so isn't relevant
; ARMT2-LABEL: t8:
; ARMT2: bl t7
@@ -214,7 +214,7 @@ entry:
define void @t9(i8* %a, i8 %b) {
entry:
-; ARM scheduler emits icmp/zext before both calls, so isn't relevant
+; COM: ARM scheduler emits icmp/zext before both calls, so isn't relevant
; ARMT2-LABEL: t9:
; ARMT2: bl f
diff --git a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
index 1ff8a39fbb8e..a7c8c46e9c3b 100644
--- a/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
+++ b/llvm/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll
@@ -12,17 +12,17 @@
;RUN: cat %t | FileCheck %s --check-prefix=T1POST
;RUN: cat %t | FileCheck %s --check-prefix=V8MBASE
-;This file contains auto generated tests for the lowering of passing structs
-;byval in the arm backend. We have tests for both packed and unpacked
-;structs at varying alignments. Each test is run for arm, thumb2 and thumb1.
-;We check for the strings in the generated object code using llvm-objdump
-;because it provides better assurance that we are generating instructions
-;for the correct architecture. Otherwise we could accidentally generate an
-;ARM instruction for THUMB1 and wouldn't detect it because the assembly
-;code representation is the same, but the object code would be generated
-;incorrectly. For each test we check for the label, a load instruction of the
-;correct form, a branch if it will be generated with a loop, and the leftover
-;cleanup if the number of bytes does not divide evenly by the store size
+; COM: This file contains auto generated tests for the lowering of passing structs
+; COM: byval in the arm backend. We have tests for both packed and unpacked
+; COM: structs at varying alignments. Each test is run for arm, thumb2 and thumb1.
+; COM: We check for the strings in the generated object code using llvm-objdump
+; COM: because it provides better assurance that we are generating instructions
+; COM: for the correct architecture. Otherwise we could accidentally generate an
+; COM: ARM instruction for THUMB1 and wouldn't detect it because the assembly
+; COM: code representation is the same, but the object code would be generated
+; COM: incorrectly. For each test we check for the label, a load instruction of the
+; COM: correct form, a branch if it will be generated with a loop, and the leftover
+; COM: cleanup if the number of bytes does not divide evenly by the store size
%struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes
declare void @use_A(%struct.A* byval)
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
index 004f6d94749d..1e17b0d7a10e 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
@@ -46,14 +46,14 @@ entry:
}
; ALL-LABEL: double_args:
-; We won't test the way the global address is calculated in this test. This is
-; just to get the register number for the other checks.
+; COM: We won't test the way the global address is calculated in this test. This is
+; COM: just to get the register number for the other checks.
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
-; The first four arguments are the same in O32/N32/N64.
-; The first argument is floating point but soft-float is enabled so floating
-; point registers are not used.
+; COM: The first four arguments are the same in O32/N32/N64.
+; COM: The first argument is floating point but soft-float is enabled so floating
+; COM: point registers are not used.
; O32-DAG: sw $4, 8([[R2]])
; O32-DAG: sw $5, 12([[R2]])
; NEW-DAG: sd $4, 8([[R2]])
@@ -62,7 +62,7 @@ entry:
; O32-DAG: sw $7, 20([[R2]])
; NEW-DAG: sd $5, 16([[R2]])
-; O32 has run out of argument registers and starts using the stack
+; COM: O32 has run out of argument registers and starts using the stack
; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 16($sp)
; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp)
; O32-DAG: sw [[R3]], 24([[R2]])
@@ -134,18 +134,18 @@ entry:
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
-; The first four arguments are the same in O32/N32/N64.
-; The first argument is floating point but soft-float is enabled so floating
-; point registers are not used.
-; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
-; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
-; aligned and occupying one slot. We'll use GCC's definition.
+; COM: The first four arguments are the same in O32/N32/N64.
+; COM: The first argument is floating point but soft-float is enabled so floating
+; COM: point registers are not used.
+; COM: MD00305 and GCC disagree on this one. MD00305 says that floats are treated
+; COM: as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
+; COM: aligned and occupying one slot. We'll use GCC's definition.
; ALL-DAG: sw $4, 4([[R2]])
; ALL-DAG: sw $5, 8([[R2]])
; ALL-DAG: sw $6, 12([[R2]])
; ALL-DAG: sw $7, 16([[R2]])
-; O32 has run out of argument registers and starts using the stack
+; COM: O32 has run out of argument registers and starts using the stack
; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
; O32-DAG: sw [[R3]], 20([[R2]])
; NEW-DAG: sw $8, 20([[R2]])
@@ -162,7 +162,7 @@ entry:
; O32-DAG: sw [[R3]], 32([[R2]])
; NEW-DAG: sw $11, 32([[R2]])
-; N32/N64 have run out of registers and start using the stack too
+; COM: N32/N64 have run out of registers and start using the stack too
; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
; O32-DAG: sw [[R3]], 36([[R2]])
; NEW-DAG: lw [[R3:\$[0-9]+]], 0($sp)
@@ -185,11 +185,11 @@ entry:
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
-; The first four arguments are the same in O32/N32/N64.
-; The first argument isn't floating point so floating point registers are not
-; used.
-; The second slot is insufficiently aligned for double on O32 so it is skipped.
-; Also, double occupies two slots on O32 and only one for N32/N64.
+; COM: The first four arguments are the same in O32/N32/N64.
+; COM: The first argument isn't floating point so floating point registers are not
+; COM: used.
+; COM: The second slot is insufficiently aligned for double on O32 so it is skipped.
+; COM: Also, double occupies two slots on O32 and only one for N32/N64.
; ALL-DAG: sb $4, 1([[R1]])
; O32-DAG: sw $6, 8([[R2]])
; O32-DAG: sw $7, 12([[R2]])
@@ -213,11 +213,11 @@ entry:
; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
-; The first four arguments are the same in O32/N32/N64.
-; The first argument isn't floating point so floating point registers are not
-; used.
-; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
-; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
-; aligned and occupying one slot. We'll use GCC's definition.
+; COM: The first four arguments are the same in O32/N32/N64.
+; COM: The first argument isn't floating point so floating point registers are not
+; COM: used.
+; COM: MD00305 and GCC disagree on this one. MD00305 says that floats are treated
+; COM: as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
+; COM: aligned and occupying one slot. We'll use GCC's definition.
; ALL-DAG: sb $4, 1([[R1]])
; ALL-DAG: sw $5, 4([[R2]])
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
index ae1a6d54bb23..4c37930d171a 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
@@ -18,14 +18,14 @@
; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s \
; RUN: | FileCheck --check-prefixes=ALL,SYM64,N64,NEW,NEWLE %s
-; Test the effect of varargs on floating point types in the non-variable part
-; of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
+; COM: Test the effect of varargs on floating point types in the non-variable part
+; COM: of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
;
-; N32/N64 are almost identical in this area so many of their checks have been
-; combined into the 'NEW' prefix (the N stands for New).
+; COM: N32/N64 are almost identical in this area so many of their checks have been
+; COM: combined into the 'NEW' prefix (the N stands for New).
;
-; On O32, varargs prevents all FPU argument register usage. This contradicts
-; the N32 handbook, but agrees with the SYSV ABI and GCC's behaviour.
+; COM: On O32, varargs prevents all FPU argument register usage. This contradicts
+; COM: the N32 handbook, but agrees with the SYSV ABI and GCC's behaviour.
@floats = global [11 x float] zeroinitializer
@doubles = global [11 x double] zeroinitializer
@@ -52,8 +52,8 @@ entry:
; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
; SYM64-DAG: daddiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
-; O32 forbids using floating point registers for the non-variable portion.
-; N32/N64 allow it.
+; COM: O32 forbids using floating point registers for the non-variable portion.
+; COM: N32/N64 allow it.
; O32BE-DAG: mtc1 $5, [[FTMP1:\$f[0-9]*[02468]+]]
; O32BE-DAG: mtc1 $4, [[FTMP2:\$f[0-9]*[13579]+]]
; O32LE-DAG: mtc1 $4, [[FTMP1:\$f[0-9]*[02468]+]]
@@ -72,10 +72,10 @@ entry:
; NEW-DAG: sd $10, 48($sp)
; NEW-DAG: sd $11, 56($sp)
-; Get the varargs pointer
-; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and 8 bytes reserved
-; for arguments 1 and 2.
-; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
+; COM: Get the varargs pointer
+; COM: O32 has 4 bytes padding, 4 bytes for the varargs pointer, and 8 bytes reserved
+; COM: for arguments 1 and 2.
+; COM: N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
; O32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 16
; O32-DAG: sw [[VAPTR]], 4($sp)
; N32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 8
@@ -133,11 +133,11 @@ entry:
; NEW-DAG: sd $11, 56($sp)
; Get the varargs pointer
-; O32 has 4 bytes padding, 4 bytes for the varargs pointer, and should have 8
-; bytes reserved for arguments 1 and 2 (the first float arg) but as discussed in
-; arguments-float.ll, GCC doesn't agree with MD00305 and treats floats as 4
-; bytes so we only have 12 bytes total.
-; N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
+; COM: O32 has 4 bytes padding, 4 bytes for the varargs pointer, and should have 8
+; COM: bytes reserved for arguments 1 and 2 (the first float arg) but as discussed in
+; COM: arguments-float.ll, GCC doesn't agree with MD00305 and treats floats as 4
+; COM: bytes so we only have 12 bytes total.
+; COM: N32/N64 has 8 bytes for the varargs pointer, and no reserved area.
; O32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 12
; O32-DAG: sw [[VAPTR]], 4($sp)
; N32-DAG: addiu [[VAPTR:\$[0-9]+]], $sp, 8
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
index e98a11a8064c..e3d794d492cb 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-hard-float.ll
@@ -58,7 +58,7 @@ entry:
; O32-DAG: sdc1 $f14, 16([[R2]])
; NEW-DAG: sdc1 $f13, 16([[R2]])
-; O32 has run out of argument registers and starts using the stack
+; COM: O32 has run out of argument registers and starts using the stack
; O32-DAG: ldc1 [[F1:\$f[0-9]+]], 16($sp)
; O32-DAG: sdc1 [[F1]], 24([[R2]])
; NEW-DAG: sdc1 $f14, 24([[R2]])
@@ -121,10 +121,10 @@ entry:
; O32-DAG: swc1 $f14, 8([[R1]])
; NEW-DAG: swc1 $f13, 8([[R1]])
-; O32 has run out of argument registers and (in theory) starts using the stack
-; I've yet to find a reference in the documentation about this but GCC uses up
-; the remaining two argument slots in the GPR's first. We'll do the same for
-; compatibility.
+; COM: O32 has run out of argument registers and (in theory) starts using the stack
+; COM: I've yet to find a reference in the documentation about this but GCC uses up
+; COM: the remaining two argument slots in the GPR's first. We'll do the same for
+; COM: compatibility.
; O32-DAG: mtc1 $6, $f0
; O32-DAG: swc1 $f0, 12([[R1]])
; NEW-DAG: swc1 $f14, 12([[R1]])
@@ -132,7 +132,7 @@ entry:
; O32-DAG: swc1 $f0, 16([[R1]])
; NEW-DAG: swc1 $f15, 16([[R1]])
-; O32 is definitely out of registers now and switches to the stack.
+; COM: O32 is definitely out of registers now and switches to the stack.
; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 16($sp)
; O32-DAG: swc1 [[F1]], 20([[R1]])
; NEW-DAG: swc1 $f16, 20([[R1]])
@@ -146,7 +146,7 @@ entry:
; O32-DAG: swc1 [[F1]], 32([[R1]])
; NEW-DAG: swc1 $f19, 32([[R1]])
-; N32/N64 have run out of registers and start using the stack too
+; COM: N32/N64 have run out of registers and start using the stack too
; O32-DAG: lwc1 [[F1:\$f[0-9]+]], 32($sp)
; O32-DAG: swc1 [[F1]], 36([[R1]])
; NEW-DAG: lwc1 [[F1:\$f[0-9]+]], 0($sp)
@@ -173,10 +173,10 @@ entry:
; The first argument is the same in O32/N32/N64.
; ALL-DAG: sb $4, 1([[R1]])
-; The first argument isn't floating point so floating point registers are not
-; used in O32, but N32/N64 will still use them.
-; The second slot is insufficiently aligned for double on O32 so it is skipped.
-; Also, double occupies two slots on O32 and only one for N32/N64.
+; COM: The first argument isn't floating point so floating point registers are not
+; COM: used in O32, but N32/N64 will still use them.
+; COM: The second slot is insufficiently aligned for double on O32 so it is skipped.
+; COM: Also, double occupies two slots on O32 and only one for N32/N64.
; O32LE-DAG: mtc1 $6, [[F1:\$f[0-9]*[02468]+]]
; O32LE-DAG: mtc1 $7, [[F2:\$f[0-9]*[13579]+]]
; O32BE-DAG: mtc1 $6, [[F2:\$f[0-9]*[13579]+]]
@@ -204,11 +204,11 @@ entry:
; The first argument is the same in O32/N32/N64.
; ALL-DAG: sb $4, 1([[R1]])
-; The first argument isn't floating point so floating point registers are not
-; used in O32, but N32/N64 will still use them.
-; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
-; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
-; aligned and occupying one slot. We'll use GCC's definition.
+; COM: The first argument isn't floating point so floating point registers are not
+; COM: used in O32, but N32/N64 will still use them.
+; COM: MD00305 and GCC disagree on this one. MD00305 says that floats are treated
+; COM: as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
+; COM: aligned and occupying one slot. We'll use GCC's definition.
; O32-DAG: mtc1 $5, $f0
; O32-DAG: swc1 $f0, 4([[R2]])
; NEW-DAG: swc1 $f13, 4([[R2]])
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
index 275f6afbf774..57f8e5360852 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
@@ -26,8 +26,8 @@ define void @fn_i16_dotdotdot_i16(i16 %a, ...) {
entry:
; ALL-LABEL: fn_i16_dotdotdot_i16:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room
+; COM: for the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -45,12 +45,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 12 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
-; fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 12 due to the 4 bytes used to store local
+; COM: variables, 4 bytes padding to maintain stack alignment, and the 4 byte
+; COM: slot for the first fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -75,11 +75,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just
+; COM: set up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due
+; COM: to byte order.
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-LE-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
@@ -141,8 +141,8 @@ define void @fn_i16_dotdotdot_i32(i16 %a, ...) {
entry:
; ALL-LABEL: fn_i16_dotdotdot_i32:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM; the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -160,12 +160,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 12 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
-; fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 12 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
+; COM: fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -190,11 +190,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-LE-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
@@ -256,8 +256,8 @@ define void @fn_i16_dotdotdot_i64(i16 %a, ...) {
entry:
; ALL-LABEL: fn_i16_dotdotdot_i64:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -275,12 +275,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 12 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
-; fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 12 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
+; COM: fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -308,11 +308,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion and copy it to the global.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion and copy it to the global.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]])
; O32-DAG: sw [[ARG1]], 8([[GV]])
@@ -378,8 +378,8 @@ define void @fn_i32_dotdotdot_i16(i32 %a, ...) {
entry:
; ALL-LABEL: fn_i32_dotdotdot_i16:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -397,12 +397,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 12 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
-; fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 12 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
+; COM: fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -427,11 +427,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-LE-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
@@ -493,8 +493,8 @@ define void @fn_i32_dotdotdot_i32(i32 %a, ...) {
entry:
; ALL-LABEL: fn_i32_dotdotdot_i32:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -512,12 +512,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 12 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
-; fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 12 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
+; COM: fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -542,11 +542,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-LE-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
@@ -608,8 +608,8 @@ define void @fn_i32_dotdotdot_i64(i32 %a, ...) {
entry:
; ALL-LABEL: fn_i32_dotdotdot_i64:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -627,12 +627,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 12 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
-; fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 12 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the 4 byte slot for the first
+; COM: fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 12
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -644,7 +644,7 @@ entry:
; ALL: teqi $zero, 1
-; Increment [[VA]] (and realign pointer for O32)
+; COM: Increment [[VA]] (and realign pointer for O32)
; O32: lw [[VA:\$[0-9]+]], 0([[SP]])
; O32-DAG: addiu [[VA_TMP0:\$[0-9]+]], [[VA]], 7
; O32-DAG: addiu [[VA_TMP1:\$[0-9]+]], $zero, -8
@@ -660,11 +660,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion and copy it to the global.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion and copy it to the global.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA_TMP2]])
; O32-DAG: sw [[ARG1]], 8([[GV]])
@@ -730,8 +730,8 @@ define void @fn_i64_dotdotdot_i16(i64 %a, ...) {
entry:
; ALL-LABEL: fn_i64_dotdotdot_i16:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -748,12 +748,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 16 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the two 4 byte slots for the
-; first fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 16 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the two 4 byte slots for the
+; COM: first fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 16
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -778,11 +778,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-LE-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
@@ -844,8 +844,8 @@ define void @fn_i64_dotdotdot_i32(i64 %a, ...) {
entry:
; ALL-LABEL: fn_i64_dotdotdot_i32:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -862,12 +862,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 16 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the two 4 byte slots for the
-; first fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 16 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the two 4 byte slots for the
+; COM: first fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 16
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -892,11 +892,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; NEW-LE-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
@@ -958,8 +958,8 @@ define void @fn_i64_dotdotdot_i64(i64 %a, ...) {
entry:
; ALL-LABEL: fn_i64_dotdotdot_i64:
-; Set up the stack with an 8-byte local area. N32/N64 must also make room for
-; the argument save area (56 bytes).
+; COM: Set up the stack with an 8-byte local area. N32/N64 must also make room for
+; COM: the argument save area (56 bytes).
; O32: addiu [[SP:\$sp]], $sp, -8
; N32: addiu [[SP:\$sp]], $sp, -64
; N64: daddiu [[SP:\$sp]], $sp, -64
@@ -976,12 +976,12 @@ entry:
; NEW-DAG: sd $6, 16([[SP]])
; NEW-DAG: sd $5, 8([[SP]])
-; Initialize variable argument pointer.
-; For O32, the offset is 16 due to the 4 bytes used to store local variables,
-; 4 bytes padding to maintain stack alignment, and the two 4 byte slots for the
-; first fixed argument.
-; For N32/N64, it is only 8 since the fixed arguments do not reserve stack
-; space.
+; COM: Initialize variable argument pointer.
+; COM: For O32, the offset is 16 due to the 4 bytes used to store local variables,
+; COM: 4 bytes padding to maintain stack alignment, and the two 4 byte slots for the
+; COM: first fixed argument.
+; COM: For N32/N64, it is only 8 since the fixed arguments do not reserve stack
+; COM: space.
; O32-DAG: addiu [[VA:\$[0-9]+]], [[SP]], 16
; O32-DAG: sw [[VA]], 0([[SP]])
@@ -1009,11 +1009,11 @@ entry:
; N64-DAG: addiu [[VA2:\$[0-9]+]], [[VA]], 8
; N64-DAG: sd [[VA2]], 0([[SP]])
-; Load the first argument from the variable portion and copy it to the global.
-; This has used the stack pointer directly rather than the [[VA]] we just set
-; up.
-; Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
-; order.
+; COM: Load the first argument from the variable portion and copy it to the global.
+; COM: This has used the stack pointer directly rather than the [[VA]] we just set
+; COM: up.
+; COM: Big-endian mode for N32/N64 must add an additional 4 to the offset due to byte
+; COM: order.
; O32-DAG: addiu [[GV:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
; O32-DAG: lw [[ARG1:\$[0-9]+]], 0([[VA]])
; O32-DAG: sw [[ARG1]], 8([[GV]])
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments.ll b/llvm/test/CodeGen/Mips/cconv/arguments.ll
index 2466d59045bb..fdf0138768ee 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments.ll
@@ -57,15 +57,15 @@ entry:
; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
; SYM64-DAG: daddiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
-; The first four arguments are the same in O32/N32/N64
+; COM: The first four arguments are the same in O32/N32/N64
; ALL-DAG: sb $4, 1([[R1]])
; ALL-DAG: sb $5, 2([[R1]])
; ALL-DAG: sb $6, 3([[R1]])
; ALL-DAG: sb $7, 4([[R1]])
-; N32/N64 get an extra four arguments in registers
-; O32 starts loading from the stack. The addresses start at 16 because space is
-; always reserved for the first four arguments.
+; COM: N32/N64 get an extra four arguments in registers
+; COM: O32 starts loading from the stack. The addresses start at 16 because space is
+; COM: always reserved for the first four arguments.
; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
; O32-DAG: sb [[R3]], 5([[R1]])
; NEW-DAG: sb $8, 5([[R1]])
@@ -79,9 +79,9 @@ entry:
; O32-DAG: sb [[R3]], 8([[R1]])
; NEW-DAG: sb $11, 8([[R1]])
-; O32/N32/N64 are accessing the stack at this point.
-; Unlike O32, N32/N64 do not reserve space for the arguments.
-; increase by 4 for O32 and 8 for N32/N64.
+; COM: O32/N32/N64 are accessing the stack at this point.
+; COM: Unlike O32, N32/N64 do not reserve space for the arguments.
+; COM: increase by 4 for O32 and 8 for N32/N64.
; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
; O32-DAG: sb [[R3]], 9([[R1]])
; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
@@ -127,19 +127,19 @@ entry:
; The first argument is the same in O32/N32/N64.
; ALL-DAG: sb $4, 1([[R1]])
-; The second slot is insufficiently aligned for i64 on O32 so it is skipped.
-; Also, i64 occupies two slots on O32 and only one for N32/N64.
+; COM: The second slot is insufficiently aligned for i64 on O32 so it is skipped.
+; COM: Also, i64 occupies two slots on O32 and only one for N32/N64.
; O32-DAG: sw $6, 8([[R2]])
; O32-DAG: sw $7, 12([[R2]])
; NEW-DAG: sd $5, 8([[R2]])
-; N32/N64 get an extra four arguments in registers and still have two left from
-; the first four.
-; O32 starts loading from the stack. The addresses start at 16 because space is
-; always reserved for the first four arguments.
-; It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll
-; accept it for now. The only IR
diff erence is that this argument has
-; anyext from i8 and align 8 on it.
+; COM: N32/N64 get an extra four arguments in registers and still have two left from
+; COM: the first four.
+; COM: O32 starts loading from the stack. The addresses start at 16 because space is
+; COM: always reserved for the first four arguments.
+; COM: It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll
+; COM: accept it for now. The only IR
diff erence is that this argument has
+; COM: anyext from i8 and align 8 on it.
; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
; O32-DAG: sb [[R3]], 2([[R1]])
; NEW-DAG: sb $6, 2([[R1]])
@@ -163,9 +163,9 @@ entry:
; O32-DAG: sw [[R3]], 20([[R2]])
; NEW-DAG: sd $11, 16([[R2]])
-; O32/N32/N64 are accessing the stack at this point.
-; Unlike O32, N32/N64 do not reserve space for the arguments.
-; increase by 4 for O32 and 8 for N32/N64.
+; COM: O32/N32/N64 are accessing the stack at this point.
+; COM: Unlike O32, N32/N64 do not reserve space for the arguments.
+; COM: increase by 4 for O32 and 8 for N32/N64.
; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp)
; O32-DAG: sb [[R3]], 7([[R1]])
; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
diff --git a/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll
index ca0794b22dcf..f0cd38034635 100644
--- a/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll
+++ b/llvm/test/CodeGen/Mips/cconv/return-hard-fp128.ll
@@ -4,8 +4,8 @@
; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; Test the fp128 returns for N32/N64 and all byte orders as specified by
-; section 5 of MD00305 (MIPS ABIs Described).
+; COM: Test the fp128 returns for N32/N64 and all byte orders as specified by
+; COM: section 5 of MD00305 (MIPS ABIs Described).
;
; O32 is not tested because long double is the same as double on O32.
;
diff --git a/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
index 43b0baa70013..abf29dce0f75 100644
--- a/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
+++ b/llvm/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
@@ -4,7 +4,7 @@
; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s
-; Test return of {fp128} agrees with de-facto N32/N64 ABI.
+; COM: Test return of {fp128} agrees with de-facto N32/N64 ABI.
@struct_fp128 = global {fp128} zeroinitializer
@@ -19,9 +19,9 @@ entry:
; O32 generates
diff erent IR so we don't test it here. It returns the struct
; indirectly.
-; Contrary to the N32/N64 ABI documentation, a struct containing a long double
-; is returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to
-; match the de facto ABI as implemented by GCC.
+; COM: Contrary to the N32/N64 ABI documentation, a struct containing a long
+; COM: double is returned in $f0, and $f1 instead of the usual $f0, and $f2.
+; COM: This is to match the de facto ABI as implemented by GCC.
; N32-DAG: lui [[R1:\$[0-9]+]], %hi(struct_fp128)
; N32-DAG: ldc1 $f0, %lo(struct_fp128)([[R1]])
; N32-DAG: addiu [[R3:\$[0-9]+]], [[R1]], %lo(struct_fp128)
diff --git a/llvm/test/CodeGen/Mips/countleading.ll b/llvm/test/CodeGen/Mips/countleading.ll
index 35933f668fb9..58d96c0ae0e4 100644
--- a/llvm/test/CodeGen/Mips/countleading.ll
+++ b/llvm/test/CodeGen/Mips/countleading.ll
@@ -6,10 +6,10 @@
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
-; Prefixes:
-; ALL - All
-; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
-; MIPS64-GT-R1 - MIPS64r1 and above
+; COM: Prefixes:
+; COM: ALL - All
+; COM: MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
+; COM: MIPS64-GT-R1 - MIPS64r1 and above
define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/divrem.ll b/llvm/test/CodeGen/Mips/divrem.ll
index 35bc96a0d03d..6b679acfe28a 100644
--- a/llvm/test/CodeGen/Mips/divrem.ll
+++ b/llvm/test/CodeGen/Mips/divrem.ll
@@ -12,17 +12,17 @@
; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK
; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK
-; FileCheck Prefixes:
-; ALL - All targets
-; ACC32 - Accumulator based multiply/divide on 32-bit targets
-; ACC64 - Same as ACC32 but only for 64-bit targets
-; GPR32 - GPR based multiply/divide on 32-bit targets
-; GPR64 - Same as GPR32 but only for 64-bit targets
-; ACC32-TRAP - Same as TRAP and ACC32 combined
-; ACC64-TRAP - Same as TRAP and ACC64 combined
-; GPR32-TRAP - Same as TRAP and GPR32 combined
-; GPR64-TRAP - Same as TRAP and GPR64 combined
-; NOCHECK - Division by zero will not be detected
+; COM: FileCheck Prefixes:
+; COM: ALL - All targets
+; COM: ACC32 - Accumulator based multiply/divide on 32-bit targets
+; COM: ACC64 - Same as ACC32 but only for 64-bit targets
+; COM: GPR32 - GPR based multiply/divide on 32-bit targets
+; COM: GPR64 - Same as GPR32 but only for 64-bit targets
+; COM: ACC32-TRAP - Same as TRAP and ACC32 combined
+; COM: ACC64-TRAP - Same as TRAP and ACC64 combined
+; COM: GPR32-TRAP - Same as TRAP and GPR32 combined
+; COM: GPR64-TRAP - Same as TRAP and GPR64 combined
+; COM: NOCHECK - Division by zero will not be detected
@g0 = common global i32 0, align 4
@g1 = common global i32 0, align 4
diff --git a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
index 50acd8ffb1eb..38213893742c 100644
--- a/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
+++ b/llvm/test/CodeGen/Mips/dynamic-stack-realignment.ll
@@ -65,7 +65,7 @@ entry:
declare void @helper_02(i32, i32, i32, i32,
i32, i32, i32, i32, i32*)
-; N32/N64 ABIs
+; COM: N32/N64 ABIs
define void @func_02() {
entry:
; GP64-LABEL: func_02:
@@ -108,7 +108,7 @@ entry:
declare void @helper_03(i32, i32, i32, i32, i32*, i32*)
-; O32 ABI
+; COM: O32 ABI
define void @func_03(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32* %b) {
entry:
; GP32-LABEL: func_03:
@@ -130,7 +130,7 @@ entry:
declare void @helper_04(i32, i32, i32, i32,
i32, i32, i32, i32, i32*, i32*)
-; N32/N64 ABIs
+; COM: N32/N64 ABIs
define void @func_04(i32 %p0, i32 %p1, i32 %p2, i32 %p3,
i32 %p4, i32 %p5, i32 %p6, i32 %p7,
i32* %b) {
@@ -153,7 +153,7 @@ entry:
; Check dynamic stack realignment in functions with variable-sized objects.
-; O32 ABI
+; COM: O32 ABI
define void @func_05(i32 %sz) {
entry:
; GP32-LABEL: func_05:
@@ -194,7 +194,7 @@ entry:
ret void
}
-; N32/N64 ABIs
+; COM: N32/N64 ABIs
define void @func_06(i32 %sz) {
entry:
; GP64-LABEL: func_06:
@@ -262,7 +262,7 @@ entry:
ret void
}
-; N32/N64 ABIs
+; COM: N32/N64 ABIs
define void @func_08(i32 %p0, i32 %p1, i32 %p2, i32 %p3,
i32 %p4, i32 %p5, i32 %p6, i32 %p7,
i32 %sz) {
diff --git a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
index 0b8e831150e6..6faa5856af2d 100644
--- a/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-operand-code.ll
@@ -5,7 +5,7 @@
; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefixes=ALL,BE32,GAS %s
-; IAS might not print in the same way since it parses the assembly.
+; COM: IAS might not print in the same way since it parses the assembly.
; RUN: llc -march=mipsel -relocation-model=pic < %s | \
; RUN: FileCheck -check-prefixes=ALL,LE32,IAS %s
; RUN: llc -march=mips -relocation-model=pic < %s | \
diff --git a/llvm/test/CodeGen/Mips/mips64muldiv.ll b/llvm/test/CodeGen/Mips/mips64muldiv.ll
index d1292be504e6..0dde12a004e7 100644
--- a/llvm/test/CodeGen/Mips/mips64muldiv.ll
+++ b/llvm/test/CodeGen/Mips/mips64muldiv.ll
@@ -3,10 +3,10 @@
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,ACC
; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR
-; FileCheck prefixes:
-; ALL - All targets
-; ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
-; GPR - Targets with register based mul/div (i.e. MIPS32r6)
+; COM: FileCheck prefixes:
+; COM: ALL - All targets
+; COM: ACC - Targets with accumulator based mul/div (i.e. pre-MIPS32r6)
+; COM: GPR - Targets with register based mul/div (i.e. MIPS32r6)
define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
index b6a8748c8e3e..c2b515521d72 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
+++ b/llvm/test/CodeGen/PowerPC/ppc64-crsave.mir
@@ -11,8 +11,9 @@
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
-# TODO FIXME: We only check the save and restores of the callee saved gpr for
-# ELF becuase AIX callee saved registers haven't been properly implemented yet.
+# COM: TODO FIXME: We only check the save and restores of the callee saved gpr
+# COM: for ELF becuase AIX callee saved registers haven't been
+# COM: properly implemented yet.
---
name: CRAllSave
@@ -77,8 +78,8 @@ body: |
; Verify the proper live-ins have been added in the prologue.
; CHECK: liveins: $x3, $x14, $cr2
- ; ELF V2 ABI allows saving only the clobbered cr fields,
- ; whereas the other ABIs do not.
+ ; COM: ELF V2 ABI allows saving only the clobbered cr fields,
+ ; COM: whereas the other ABIs do not.
; SAVEONE: $x12 = MFOCRF8 killed $cr2
; SAVEALL: $x12 = MFCR8 implicit killed $cr2
diff --git a/llvm/test/CodeGen/X86/avx-cast.ll b/llvm/test/CodeGen/X86/avx-cast.ll
index 92d9319a1877..5a740b0fb901 100644
--- a/llvm/test/CodeGen/X86/avx-cast.ll
+++ b/llvm/test/CodeGen/X86/avx-cast.ll
@@ -24,7 +24,7 @@ define <4 x double> @castB(<2 x double> %m) nounwind uwtable readnone ssp {
ret <4 x double> %shuffle.i
}
-; AVX2 is needed for integer types.
+; COM: AVX2 is needed for integer types.
define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
; AVX-LABEL: castC:
diff --git a/llvm/test/CodeGen/X86/fp-intrinsics.ll b/llvm/test/CodeGen/X86/fp-intrinsics.ll
index 27f198168e38..5b3cebccc735 100644
--- a/llvm/test/CodeGen/X86/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/fp-intrinsics.ll
@@ -919,8 +919,8 @@ entry:
; Verify that fptosi(%x) isn't simplified when the rounding mode is
; unknown.
; Verify that no gross errors happen.
-; FIXME: The SSE/AVX code does not raise an invalid exception for all values
-; that don't fit in i8.
+; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all
+; COM: value sthat don't fit in i8.
define i8 @f20s8(double %x) #0 {
; X87-LABEL: f20s8:
; X87: # %bb.0: # %entry
@@ -966,8 +966,8 @@ entry:
; Verify that fptosi(%x) isn't simplified when the rounding mode is
; unknown.
; Verify that no gross errors happen.
-; FIXME: The SSE/AVX code does not raise an invalid exception for all values
-; that don't fit in i16.
+; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all
+; COM: values that don't fit in i16.
define i16 @f20s16(double %x) #0 {
; X87-LABEL: f20s16:
; X87: # %bb.0: # %entry
@@ -1188,11 +1188,11 @@ entry:
ret i128 %result
}
-; Verify that fptoui(%x) isn't simplified when the rounding mode is
-; unknown.
-; Verify that no gross errors happen.
-; FIXME: The SSE/AVX code does not raise an invalid exception for all values
-; that don't fit in i8.
+; COM: Verify that fptoui(%x) isn't simplified when the rounding mode is
+; COM: unknown.
+; COM: Verify that no gross errors happen.
+; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all values
+; COM: that don't fit in i8.
define i8 @f20u8(double %x) #0 {
; X87-LABEL: f20u8:
; X87: # %bb.0: # %entry
@@ -1237,8 +1237,8 @@ entry:
; Verify that fptoui(%x) isn't simplified when the rounding mode is
; unknown.
; Verify that no gross errors happen.
-; FIXME: The SSE/AVX code does not raise an invalid exception for all values
-; that don't fit in i16.
+; COM: FIXME: The SSE/AVX code does not raise an invalid exception for all
+; COM: values that don't fit in i16.
define i16 @f20u16(double %x) #0 {
; X87-LABEL: f20u16:
; X87: # %bb.0: # %entry
@@ -1285,8 +1285,8 @@ entry:
; Verify that fptoui(%x) isn't simplified when the rounding mode is
; unknown.
; Verify that no gross errors happen.
-; FIXME: The X87/SSE/AVX1 code does not raise an invalid exception for all
-; values that don't fit in i32. The AVX512 code does.
+; COM: FIXME: The X87/SSE/AVX1 code does not raise an invalid exception for all
+; COM: values that don't fit in i32. The AVX512 code does.
define i32 @f20u(double %x) #0 {
; X87-LABEL: f20u:
; X87: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/X86/splat-for-size.ll b/llvm/test/CodeGen/X86/splat-for-size.ll
index da68f069b078..69a86c6b7e13 100644
--- a/llvm/test/CodeGen/X86/splat-for-size.ll
+++ b/llvm/test/CodeGen/X86/splat-for-size.ll
@@ -5,7 +5,7 @@
; Check constant loads of every 128-bit and 256-bit vector type
; for size optimization using splat ops available with AVX and AVX2.
-; There is no AVX broadcast from double to 128-bit vector because movddup has been around since SSE3 (grrr).
+; COM: There is no AVX broadcast from double to 128-bit vector because movddup has been around since SSE3 (grrr).
define <2 x double> @splat_v2f64(<2 x double> %x) #0 {
; CHECK-LABEL: splat_v2f64:
; CHECK: # %bb.0:
@@ -88,8 +88,9 @@ define <8 x float> @splat_v8f32_pgso(<8 x float> %x) !prof !14 {
ret <8 x float> %add
}
-; AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit value.
-; We also generate vmovddup for AVX2 because it's one byte smaller than vpbroadcastq.
+; COM: AVX can't do integer splats, so fake it: use vmovddup to splat 64-bit
+; COM: value. We also generate vmovddup for AVX2 because it's one byte smaller
+; COM: than vpbroadcastq.
define <2 x i64> @splat_v2i64(<2 x i64> %x) #1 {
; AVX-LABEL: splat_v2i64:
; AVX: # %bb.0:
@@ -124,8 +125,8 @@ define <2 x i64> @splat_v2i64_pgso(<2 x i64> %x) !prof !14 {
ret <2 x i64> %add
}
-; AVX can't do 256-bit integer ops, so we split this into two 128-bit vectors,
-; and then we fake it: use vmovddup to splat 64-bit value.
+; COM: AVX can't do 256-bit integer ops, so we split this into two 128-bit
+; COM: vectors, and then we fake it: use vmovddup to splat 64-bit value.
define <4 x i64> @splat_v4i64(<4 x i64> %x) #0 {
; AVX-LABEL: splat_v4i64:
; AVX: # %bb.0:
@@ -166,7 +167,7 @@ define <4 x i64> @splat_v4i64_pgso(<4 x i64> %x) !prof !14 {
ret <4 x i64> %add
}
-; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
+; COM: AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
define <4 x i32> @splat_v4i32(<4 x i32> %x) #1 {
; AVX-LABEL: splat_v4i32:
; AVX: # %bb.0:
@@ -199,7 +200,7 @@ define <4 x i32> @splat_v4i32_pgso(<4 x i32> %x) !prof !14 {
ret <4 x i32> %add
}
-; AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
+; COM: AVX can't do integer splats, so fake it: use vbroadcastss to splat 32-bit value.
define <8 x i32> @splat_v8i32(<8 x i32> %x) #0 {
; AVX-LABEL: splat_v8i32:
; AVX: # %bb.0:
@@ -238,7 +239,7 @@ define <8 x i32> @splat_v8i32_pgso(<8 x i32> %x) !prof !14 {
ret <8 x i32> %add
}
-; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
+; COM: AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
define <8 x i16> @splat_v8i16(<8 x i16> %x) #1 {
; AVX-LABEL: splat_v8i16:
; AVX: # %bb.0:
@@ -269,7 +270,7 @@ define <8 x i16> @splat_v8i16_pgso(<8 x i16> %x) !prof !14 {
ret <8 x i16> %add
}
-; AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
+; COM: AVX can't do integer splats, and there's no broadcast fakery for 16-bit. Could use pshuflw, etc?
define <16 x i16> @splat_v16i16(<16 x i16> %x) #0 {
; AVX-LABEL: splat_v16i16:
; AVX: # %bb.0:
@@ -308,7 +309,7 @@ define <16 x i16> @splat_v16i16_pgso(<16 x i16> %x) !prof !14 {
ret <16 x i16> %add
}
-; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
+; COM: AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
define <16 x i8> @splat_v16i8(<16 x i8> %x) #1 {
; AVX-LABEL: splat_v16i8:
; AVX: # %bb.0:
@@ -339,7 +340,7 @@ define <16 x i8> @splat_v16i8_pgso(<16 x i8> %x) !prof !14 {
ret <16 x i8> %add
}
-; AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
+; COM: AVX can't do integer splats, and there's no broadcast fakery for 8-bit. Could use pshufb, etc?
define <32 x i8> @splat_v32i8(<32 x i8> %x) #0 {
; AVX-LABEL: splat_v32i8:
; AVX: # %bb.0:
@@ -378,9 +379,9 @@ define <32 x i8> @splat_v32i8_pgso(<32 x i8> %x) !prof !14 {
ret <32 x i8> %add
}
-; PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
-; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
-; loadi64 with multiple uses.
+; COM: PR23259: Verify that ISel doesn't crash with a 'fatal error in backend'
+; COM: due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
+; COM: loadi64 with multiple uses.
@A = common global <3 x i64> zeroinitializer, align 32
diff --git a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
index bd037d7079b4..f14a6853b17e 100644
--- a/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
+++ b/llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll
@@ -8,9 +8,9 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
-; Ensure that the backend no longer emits unnecessary vector insert
-; instructions immediately after SSE scalar fp instructions
-; like addss or mulss.
+; COM: Ensure that the backend no longer emits unnecessary vector insert
+; COM: instructions immediately after SSE scalar fp instructions like addss or
+; COM: mulss.
define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test_add_ss:
@@ -635,8 +635,8 @@ define <2 x double> @blend_div_sd(<2 x double> %a, double %b) {
ret <2 x double> %shuf
}
-; Ensure that the backend selects SSE/AVX scalar fp instructions
-; from a packed fp instruction plus a vector insert.
+; COM: Ensure that the backend selects SSE/AVX scalar fp instructions
+; COM: from a packed fp instruction plus a vector insert.
define <4 x float> @insert_test_add_ss(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: insert_test_add_ss:
diff --git a/llvm/test/CodeGen/X86/vec_shift6.ll b/llvm/test/CodeGen/X86/vec_shift6.ll
index 214a4c8598d6..ff93a7edd854 100644
--- a/llvm/test/CodeGen/X86/vec_shift6.ll
+++ b/llvm/test/CodeGen/X86/vec_shift6.ll
@@ -89,9 +89,9 @@ define <4 x i32> @test4(<4 x i32> %a) {
ret <4 x i32> %shl
}
-; If we have AVX/SSE2 but not AVX2, verify that the following shift is split
-; into two pmullw instructions. With AVX2, the test case below would produce
-; a single vpmullw.
+; COM: If we have AVX/SSE2 but not AVX2, verify that the following shift is
+; COM: split into two pmullw instructions. With AVX2, the test case below would
+; COM: produce a single vpmullw.
define <16 x i16> @test5(<16 x i16> %a) {
; SSE-LABEL: test5:
@@ -109,9 +109,9 @@ define <16 x i16> @test5(<16 x i16> %a) {
ret <16 x i16> %shl
}
-; If we have AVX/SSE4.1 but not AVX2, verify that the following shift is split
-; into two pmulld instructions. With AVX2, the test case below would produce
-; a single vpsllvd instead.
+; COM: If we have AVX/SSE4.1 but not AVX2, verify that the following shift is
+; COM: split into two pmulld instructions. With AVX2, the test case below would
+; COM: produce a single vpsllvd instead.
define <8 x i32> @test6(<8 x i32> %a) {
; SSE2-LABEL: test6:
@@ -148,9 +148,9 @@ define <8 x i32> @test6(<8 x i32> %a) {
ret <8 x i32> %shl
}
-; With AVX2 and AVX512, the test case below should produce a sequence of
-; two vpmullw instructions. On SSE2 instead, we split the shift in four
-; parts and then we convert each part into a pmullw.
+; COM: With AVX2 and AVX512, the test case below should produce a sequence of
+; COM: two vpmullw instructions. On SSE2 instead, we split the shift in four
+; COM: parts and then we convert each part into a pmullw.
define <32 x i16> @test7(<32 x i16> %a) {
; SSE-LABEL: test7:
@@ -183,8 +183,8 @@ define <32 x i16> @test7(<32 x i16> %a) {
ret <32 x i16> %shl
}
-; Similar to test7; the
diff erence is that with AVX512 support
-; we only produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq.
+; COM: Similar to test7; the
diff erence is that with AVX512 support we only
+; COM: produce a single vpsllvd/vpsllvq instead of a pair of vpsllvd/vpsllvq.
define <16 x i32> @test8(<16 x i32> %a) {
; SSE2-LABEL: test8:
@@ -243,7 +243,8 @@ define <16 x i32> @test8(<16 x i32> %a) {
ret <16 x i32> %shl
}
-; The shift from 'test9' gets shifted separately and blended if we don't have AVX2/AVX512f support.
+; COM: The shift from 'test9' gets shifted separately and blended if we don't
+; COM: have AVX2/AVX512f support.
define <8 x i64> @test9(<8 x i64> %a) {
; SSE2-LABEL: test9:
diff --git a/llvm/test/CodeGen/X86/vector-compare-combines.ll b/llvm/test/CodeGen/X86/vector-compare-combines.ll
index 722de1009489..6279b2d5971a 100644
--- a/llvm/test/CodeGen/X86/vector-compare-combines.ll
+++ b/llvm/test/CodeGen/X86/vector-compare-combines.ll
@@ -2,8 +2,8 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
-; If we have SSE/AVX intrinsics in the code, we miss obvious combines
-; unless we do them late on X86-specific nodes.
+; COM: If we have SSE/AVX intrinsics in the code, we miss obvious combines
+; COM: unless we do them late on X86-specific nodes.
declare <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32>, <4 x i32>)
diff --git a/llvm/test/CodeGen/X86/vector-narrow-binop.ll b/llvm/test/CodeGen/X86/vector-narrow-binop.ll
index d76f0dc54458..a6ae86e4993b 100644
--- a/llvm/test/CodeGen/X86/vector-narrow-binop.ll
+++ b/llvm/test/CodeGen/X86/vector-narrow-binop.ll
@@ -6,8 +6,9 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
-; AVX1 has support for 256-bit bitwise logic because the FP variants were included.
-; If using those ops requires extra insert/extract though, it's probably not worth it.
+; COM: AVX1 has support for 256-bit bitwise logic because the FP variants were
+; COM: included. If using those ops requires extra insert/extract though, it's
+; COM: probably not worth it.
define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
; SSE-LABEL: PR32790:
diff --git a/llvm/test/DebugInfo/COFF/vframe-fpo.ll b/llvm/test/DebugInfo/COFF/vframe-fpo.ll
index 20b3a437d27b..76e25d2fb19f 100644
--- a/llvm/test/DebugInfo/COFF/vframe-fpo.ll
+++ b/llvm/test/DebugInfo/COFF/vframe-fpo.ll
@@ -49,7 +49,7 @@
; ASM: movl $2, {{.*}}
; ASM: movl $3, {{.*}}
-; ASM that store-to-push conversion fires.
+; COM: ASM that store-to-push conversion fires.
; ASM: pushl
; ASM-NEXT: pushl
; ASM-NEXT: calll "?f@@YAXAAH0 at Z"
diff --git a/llvm/test/DebugInfo/X86/debug-info-static-member.ll b/llvm/test/DebugInfo/X86/debug-info-static-member.ll
index 5e2f46686bd6..af5c6816c78d 100644
--- a/llvm/test/DebugInfo/X86/debug-info-static-member.ll
+++ b/llvm/test/DebugInfo/X86/debug-info-static-member.ll
@@ -101,9 +101,9 @@ attributes #1 = { nounwind readnone }
!32 = !DILocation(line: 21, scope: !26)
!33 = !DILocation(line: 22, scope: !26)
-; PRESENT verifies that static member declarations have these attributes:
-; external, declaration, accessibility, and either DW_AT_linkage_name
-; (for variables) or DW_AT_const_value (for constants).
+; COM: PRESENT verifies that static member declarations have these attributes:
+; COM: external, declaration, accessibility, and either DW_AT_linkage_name (for
+; COM: variables) or DW_AT_const_value (for constants).
;
; PRESENT: .debug_info contents:
; PRESENT: DW_TAG_variable
@@ -204,9 +204,9 @@ attributes #1 = { nounwind readnone }
; DARWINP-NEXT: DW_AT_location
; DARWINP-NEXT: DW_AT_linkage_name {{.*}} "_ZN1C1cE"
-; ABSENT verifies that static member declarations do not have either
-; DW_AT_location or DW_AT_data_member_location; also, variables do not
-; have DW_AT_const_value and constants do not have DW_AT_linkage_name.
+; COM: ABSENT verifies that static member declarations do not have either
+; COM: DW_AT_location or DW_AT_data_member_location; also, variables do not
+; COM: have DW_AT_const_value and constants do not have DW_AT_linkage_name.
;
; ABSENT: .debug_info contents:
; ABSENT: DW_TAG_member
diff --git a/llvm/test/FileCheck/dump-input-annotations.txt b/llvm/test/FileCheck/dump-input-annotations.txt
index f4f0d3ca6022..c75e7b4a7bdd 100644
--- a/llvm/test/FileCheck/dump-input-annotations.txt
+++ b/llvm/test/FileCheck/dump-input-annotations.txt
@@ -408,11 +408,11 @@
; RUN: echo 'CHECK-DAG: def' >> %t.chk
; Prefixes used here:
-; DAG = quiet, -v, or -vv
-; DAG-Q = quiet
-; DAG-V = -v or -vv (-vv implies -v)
-; DAG-VQ = -v and not -vv
-; DAG-VV = -vv
+; COM: DAG = quiet, -v, or -vv
+; COM: DAG-Q = quiet
+; COM: DAG-V = -v or -vv (-vv implies -v)
+; COM: DAG-VQ = -v and not -vv
+; COM: DAG-VV = -vv
; RUN: %ProtectFileCheckOutput \
; RUN: not FileCheck -dump-input=always -input-file %t.in %t.chk 2>&1 \
diff --git a/llvm/test/FileCheck/var-scope.txt b/llvm/test/FileCheck/var-scope.txt
index e45610b138ef..7005e21e8cee 100644
--- a/llvm/test/FileCheck/var-scope.txt
+++ b/llvm/test/FileCheck/var-scope.txt
@@ -1,8 +1,8 @@
-; Test that variables not starting with dollar sign get undefined after a
-; CHECK-LABEL directive iff --enable-var-scope is used.
+; COM: Test that variables not starting with dollar sign get undefined after a
+; COM: CHECK-LABEL directive iff --enable-var-scope is used.
-; Reference run: variables remain defined at all time when not using
-; --enable-var-scope option.
+; COM: Reference run: variables remain defined at all time when not using
+; COM: --enable-var-scope option.
RUN: FileCheck --check-prefixes CHECK,LOCAL3,GLOBAL --input-file %s %s
RUN: FileCheck --check-prefixes CHECK,GLOBAL --enable-var-scope --input-file %s %s
diff --git a/llvm/test/MC/AsmParser/expr-shr.s b/llvm/test/MC/AsmParser/expr-shr.s
index 105858cd6a8d..8a536f121678 100644
--- a/llvm/test/MC/AsmParser/expr-shr.s
+++ b/llvm/test/MC/AsmParser/expr-shr.s
@@ -6,7 +6,7 @@
// CHECK: .quad 3
-// MSVC does AShr.
+// COM: MSVC does AShr.
// MSVC: .quad -1
.quad (~0 >> 62)
diff --git a/llvm/test/MC/Mips/relocation-n64.s b/llvm/test/MC/Mips/relocation-n64.s
index 155ac20653a9..ff7f87325073 100644
--- a/llvm/test/MC/Mips/relocation-n64.s
+++ b/llvm/test/MC/Mips/relocation-n64.s
@@ -11,14 +11,14 @@
// Test that we produce the correct relocation.
// FIXME: move more relocation only tests here.
-// Check prefixes:
-// RELOC - Check the relocation in the object.
-// FIXUP - Check the fixup on the instruction.
-// ENCBE - Check the big-endian encoding on the instruction.
-// ENCLE - Check the little-endian encoding on the instruction.
-// ????? - Placeholder. Relocation is defined but the way of generating it is
-// unknown.
-// FIXME - Placeholder. Generation method is known but doesn't work.
+// COM: Check prefixes:
+// COM: RELOC - Check the relocation in the object.
+// COM: FIXUP - Check the fixup on the instruction.
+// COM: ENCBE - Check the big-endian encoding on the instruction.
+// COM: ENCLE - Check the little-endian encoding on the instruction.
+// COM: ????? - Placeholder. Relocation is defined but the way of generating it is
+// COM: unknown.
+// COM: FIXME - Placeholder. Generation method is known but doesn't work.
// DATA-LABEL: Name: .text
// DATA: SectionData (
diff --git a/llvm/test/MC/Mips/relocation.s b/llvm/test/MC/Mips/relocation.s
index 0ff450b24a00..7bccb748b2de 100644
--- a/llvm/test/MC/Mips/relocation.s
+++ b/llvm/test/MC/Mips/relocation.s
@@ -11,14 +11,14 @@
// Test that we produce the correct relocation.
// FIXME: move more relocation only tests here.
-// Check prefixes:
-// RELOC - Check the relocation in the object.
-// FIXUP - Check the fixup on the instruction.
-// ENCBE - Check the big-endian encoding on the instruction.
-// ENCLE - Check the little-endian encoding on the instruction.
-// ????? - Placeholder. Relocation is defined but the way of generating it is
-// unknown.
-// FIXME - Placeholder. Generation method is known but doesn't work.
+// COM: Check prefixes:
+// COM: RELOC - Check the relocation in the object.
+// COM: FIXUP - Check the fixup on the instruction.
+// COM: ENCBE - Check the big-endian encoding on the instruction.
+// COM: ENCLE - Check the little-endian encoding on the instruction.
+// COM: ????? - Placeholder. Relocation is defined but the way of generating it is
+// COM: unknown.
+// COM: FIXME - Placeholder. Generation method is known but doesn't work.
// RELOC-LABEL: .rel.text {
// DATA-LABEL: Name: .text
diff --git a/llvm/test/MC/RISCV/compressed-relocations.s b/llvm/test/MC/RISCV/compressed-relocations.s
index 31c398ef84ed..dfcbbef83811 100644
--- a/llvm/test/MC/RISCV/compressed-relocations.s
+++ b/llvm/test/MC/RISCV/compressed-relocations.s
@@ -5,10 +5,10 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
-# Check prefixes:
-# RELOC - Check the relocation in the object.
-# FIXUP - Check the fixup on the instruction.
-# INSTR - Check the instruction is handled properly by the ASMPrinter
+# COM: Check prefixes:
+# COM: RELOC - Check the relocation in the object.
+# COM: FIXUP - Check the fixup on the instruction.
+# COM: INSTR - Check the instruction is handled properly by the ASMPrinter
c.jal foo
# A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal).
# RELOC: R_RISCV_JAL
diff --git a/llvm/test/MC/RISCV/relocations.s b/llvm/test/MC/RISCV/relocations.s
index 10a28903906a..f60eedf81b73 100644
--- a/llvm/test/MC/RISCV/relocations.s
+++ b/llvm/test/MC/RISCV/relocations.s
@@ -3,10 +3,10 @@
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
-# Check prefixes:
-# RELOC - Check the relocation in the object.
-# FIXUP - Check the fixup on the instruction.
-# INSTR - Check the instruction is handled properly by the ASMPrinter
+# COM: Check prefixes:
+# COM: RELOC - Check the relocation in the object.
+# COM: FIXUP - Check the fixup on the instruction.
+# COM: INSTR - Check the instruction is handled properly by the ASMPrinter
.long foo
# RELOC: R_RISCV_32 foo
diff --git a/llvm/test/MC/RISCV/rv32b-aliases-valid.s b/llvm/test/MC/RISCV/rv32b-aliases-valid.s
index 00404c6162ed..fe1948e02209 100644
--- a/llvm/test/MC/RISCV/rv32b-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv32b-aliases-valid.s
@@ -9,11 +9,11 @@
# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
-# The following check prefixes are used in this test:
-# CHECK-S-OBJ Match both the .s and objdumped object output with
-# aliases enabled
-# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
-# aliases disabled
+# COM: The following check prefixes are used in this test:
+# COM: CHECK-S-OBJ Match both the .s and objdumped object output with
+# COM: aliases enabled
+# COM: CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# COM: aliases disabled
# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
# CHECK-S-OBJ: zext.b t0, t1
diff --git a/llvm/test/MC/RISCV/rv64b-aliases-valid.s b/llvm/test/MC/RISCV/rv64b-aliases-valid.s
index 02f8a8517613..b6f6cf51b27c 100644
--- a/llvm/test/MC/RISCV/rv64b-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rv64b-aliases-valid.s
@@ -9,11 +9,11 @@
# RUN: | llvm-objdump -d -r --mattr=+experimental-b - \
# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
-# The following check prefixes are used in this test:
-# CHECK-S-OBJ Match both the .s and objdumped object output with
-# aliases enabled
-# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
-# aliases disabled
+# COM: The following check prefixes are used in this test:
+# COM: CHECK-S-OBJ Match both the .s and objdumped object output with
+# COM: aliases enabled
+# COM: CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# COM: aliases disabled
# CHECK-S-OBJ-NOALIAS: andi t0, t1, 255
# CHECK-S-OBJ: zext.b t0, t1
diff --git a/llvm/test/MC/RISCV/rva-aliases-valid.s b/llvm/test/MC/RISCV/rva-aliases-valid.s
index a33b9ffd3cb4..d003dafd8843 100644
--- a/llvm/test/MC/RISCV/rva-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rva-aliases-valid.s
@@ -19,15 +19,15 @@
# RUN: | llvm-objdump -d --mattr=+a - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
-# The following check prefixes are used in this test:
-# CHECK-S Match the .s output with aliases enabled
-# CHECK-S-NOALIAS Match the .s output with aliases disabled
-# CHECK-OBJ Match the objdumped object output with aliases enabled
-# CHECK-OBJ-NOALIAS Match the objdumped object output with aliases enabled
-# CHECK-S-OBJ Match both the .s and objdumped object output with
-# aliases enabled
-# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
-# aliases disabled
+# COM: The following check prefixes are used in this test:
+# COM: CHECK-S Match the .s output with aliases enabled
+# COM: CHECK-S-NOALIAS Match the .s output with aliases disabled
+# COM: CHECK-OBJ Match the objdumped object output with aliases enabled
+# COM: CHECK-OBJ-NOALIAS Match the objdumped object output with aliases enabled
+# COM: CHECK-S-OBJ Match both the .s and objdumped object output with
+# COM: aliases enabled
+# COM: CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# COM: aliases disabled
# The below tests for lr.w, sc.w and amo*.w, using `0(reg)` are actually
# implemented using a custom parser, but we test them as if they're aliases.
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
index a78efd48fb3d..4b6414bffc8c 100644
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -19,15 +19,15 @@
# RUN: | llvm-objdump -d -r - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
-# The following check prefixes are used in this test:
-# CHECK-S Match the .s output with aliases enabled
-# CHECK-S-NOALIAS Match the .s output with aliases disabled
-# CHECK-OBJ Match the objdumped object output with aliases enabled
-# CHECK-OBJ-NOALIAS Match the objdumped object output with aliases enabled
-# CHECK-S-OBJ Match both the .s and objdumped object output with
-# aliases enabled
-# CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
-# aliases disabled
+# COM: The following check prefixes are used in this test:
+# COM: CHECK-S Match the .s output with aliases enabled
+# COM: CHECK-S-NOALIAS Match the .s output with aliases disabled
+# COM: CHECK-OBJ Match the objdumped object output with aliases enabled
+# COM: CHECK-OBJ-NOALIAS Match the objdumped object output with aliases enabled
+# COM: CHECK-S-OBJ Match both the .s and objdumped object output with
+# COM: aliases enabled
+# COM: CHECK-S-OBJ-NOALIAS Match both the .s and objdumped object output with
+# COM: aliases disabled
# TODO la
# TODO lb lh lw
diff --git a/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll b/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
index 76e497bd68fc..689df60de0fe 100644
--- a/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
+++ b/llvm/test/Transforms/InstCombine/double-float-shrink-2.ll
@@ -95,8 +95,8 @@ define float @test_shrink_libcall_trunc(float %C) {
ret float %F
}
-; This is replaced with the intrinsic, which does the right thing on
-; CHECK platforms.
+; COM: This is replaced with the intrinsic, which does the right thing on CHECK
+; COM: platforms.
define float @test_shrink_libcall_fabs(float %C) {
; CHECK-LABEL: @test_shrink_libcall_fabs(
; CHECK-NEXT: [[F:%.*]] = call float @llvm.fabs.f32(float [[C:%.*]])
diff --git a/llvm/test/Transforms/LoopFusion/cannot_fuse.ll b/llvm/test/Transforms/LoopFusion/cannot_fuse.ll
index db099c990cd3..413838eef2db 100644
--- a/llvm/test/Transforms/LoopFusion/cannot_fuse.ll
+++ b/llvm/test/Transforms/LoopFusion/cannot_fuse.ll
@@ -3,7 +3,7 @@
@B = common global [1024 x i32] zeroinitializer, align 16
-; CHECK that the two candidates for fusion are placed into separate candidate
+; Check that the two candidates for fusion are placed into separate candidate
; sets because they are not control flow equivalent.
; CHECK: Performing Loop Fusion on function non_cfe
diff --git a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
index 49d3e89b702f..ddee3f653930 100644
--- a/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
+++ b/llvm/test/tools/llvm-objdump/ELF/dynamic-section-machine-specific.test
@@ -1,6 +1,6 @@
## In this test we test how machine-specific dynamic tags are dumped.
-## Case 1: Test that hexagon machine-specific tags can be dumped.
+## COM: Case 1: Test that hexagon machine-specific tags can be dumped.
# RUN: yaml2obj --docnum=1 -o %t.hex %s
# RUN: llvm-objdump -p %t.hex | FileCheck %s --check-prefix=HEXAGON
@@ -35,8 +35,8 @@ ProgramHeaders:
Sections:
- Section: .dynamic
-## Case 2: Test that MIPS machine-specific tags can be dumped.
-## MIPS has a few long tag names. Show that we indent columns properly.
+## COM: Case 2: Test that MIPS machine-specific tags can be dumped.
+## COM: MIPS has a few long tag names. Show that we indent columns properly.
# RUN: yaml2obj --docnum=2 -o %t.mips %s
# RUN: llvm-objdump -p %t.mips | FileCheck %s --strict-whitespace --match-full-lines --check-prefix=MIPS
@@ -197,7 +197,7 @@ ProgramHeaders:
Sections:
- Section: .dynamic
-## Case 3: Test that PPC machine-specific tags can be dumped.
+## COM: Case 3: Test that PPC machine-specific tags can be dumped.
# RUN: yaml2obj --docnum=3 -o %t.ppc %s
# RUN: llvm-objdump -p %t.ppc | FileCheck %s --check-prefix=PPC
@@ -229,7 +229,7 @@ ProgramHeaders:
Sections:
- Section: .dynamic
-## Case 4: Test that PPC64 machine-specific tags can be dumped.
+## COM: Case 4: Test that PPC64 machine-specific tags can be dumped.
# RUN: yaml2obj --docnum=4 -o %t.ppc64 %s
# RUN: llvm-objdump -p %t.ppc64 | FileCheck %s --check-prefix=PPC64
@@ -258,7 +258,7 @@ ProgramHeaders:
Sections:
- Section: .dynamic
-## Case 5: Test that AARCH64 machine-specific tags can be dumped.
+## COM: Case 5: Test that AARCH64 machine-specific tags can be dumped.
# RUN: yaml2obj --docnum=5 -o %t.aarch64 %s
# RUN: llvm-objdump -p %t.aarch64 | FileCheck %s --check-prefix=AARCH64
diff --git a/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test b/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test
index d1f35306afb2..627626f1bfe2 100644
--- a/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test
+++ b/llvm/test/tools/llvm-readobj/ELF/RISCV/section-types.test
@@ -1,5 +1,5 @@
-## Show that all RISCV specific section types are properly printed for both
-## LLVM and GNU styles.
+## COM: Show that all RISCV specific section types are properly printed for both
+## COM: LLVM and GNU styles.
# RUN: yaml2obj %s -o %t-riscv.o
# RUN: llvm-readobj --section-headers %t-riscv.o | FileCheck %s --check-prefix=LLVM
diff --git a/llvm/test/tools/llvm-readobj/ELF/section-types.test b/llvm/test/tools/llvm-readobj/ELF/section-types.test
index 8718f5894c68..ecf0d7e34ed8 100644
--- a/llvm/test/tools/llvm-readobj/ELF/section-types.test
+++ b/llvm/test/tools/llvm-readobj/ELF/section-types.test
@@ -1,5 +1,5 @@
-# Show that all regular section types are properly printed for both LLVM and
-# GNU styles.
+# COM: Show that all regular section types are properly printed for both LLVM and
+# COM: GNU styles.
# RUN: yaml2obj %s -o %t-basic.o
# RUN: llvm-readobj --section-headers %t-basic.o | FileCheck %s --check-prefix=LLVM
diff --git a/llvm/test/tools/llvm-readobj/ELF/symbol-binding.test b/llvm/test/tools/llvm-readobj/ELF/symbol-binding.test
index bfd269882f62..6aba0c335e5f 100644
--- a/llvm/test/tools/llvm-readobj/ELF/symbol-binding.test
+++ b/llvm/test/tools/llvm-readobj/ELF/symbol-binding.test
@@ -1,5 +1,5 @@
-# Show that llvm-readobj can print symbol bindings correctly for both LLVM and
-# GNU styles, including for symbol bindings that are not recognised.
+# COM: Show that llvm-readobj can print symbol bindings correctly for both LLVM and
+# COM: GNU styles, including for symbol bindings that are not recognised.
# RUN: yaml2obj %s -o %t
# RUN: llvm-readobj --symbols --dyn-symbols %t | FileCheck %s --check-prefix=LLVM
More information about the llvm-commits
mailing list