[PATCH] D78494: [AMDGPU][CODEGEN] Added 'A' constraint for inline assembler

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

I guess the fundamental problem for the 16-bit immediate case is you can't know the use instruction's context. You're really accepting something that's not an inline immediate in the use context, but you have no way of knowing that.



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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10899
+  } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Op)) {
+    Val = C->getValueAPF().bitcastToAPInt().getSExtValue();
+    IsConst = true;
----------------
This should be getZExtValue? It looks like the tests worked correctly here, but not sure why it didn't matter


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https://reviews.llvm.org/D78494