[PATCH] D80367: [RISCV][MC] Print absolute targets of branch instructions

[Simon Cook via Phabricator via llvm-commits]

simoncook created this revision.
simoncook added reviewers: asb, MaskRay.
Herald added subscribers: llvm-commits, evandro, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, johnrusso, rbar, hiraditya, emaste.
Herald added a reviewer: espindola.
Herald added a project: LLVM.

This changes the output of branch/jump instructions to show the absolute
addresses of targets of branch and jump instructions (in hexadecimal,
better matching GNU objdump output)

  llvm-objdump -d output (before)
         0: 6f 00 00 00                   j       0
         4: 63 12 00 00                   bnez    zero, 4
         8: 6f f0 df ff                   j       -4
  
  llvm-objdump -d output (after)
         0: 6f 00 00 00                   j       0x0
         4: 63 12 00 00                   bnez    zero, 0x8
         8: 6f f0 df ff                   j       0x4

In RISC-V these operands are not noted as OPERAND_PCREL, and the backend
uses this field to store other information, I have extended TableGen to
handle this case.

All RISC-V MC tests have been updated to check for the correct output
as presented by both llvm-mc and llvm-objdump.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80367

Files:
  lld/test/ELF/riscv-branch.s
  lld/test/ELF/riscv-jal.s
  lld/test/ELF/riscv-undefined-weak.s
  llvm/include/llvm/Target/Target.td
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/test/CodeGen/RISCV/compress.ll
  llvm/test/MC/Disassembler/RISCV/branch-targets.txt
  llvm/test/MC/RISCV/compress-cjal.s
  llvm/test/MC/RISCV/compress-rv32i.s
  llvm/test/MC/RISCV/fixups-compressed.s
  llvm/test/MC/RISCV/fixups.s
  llvm/test/MC/RISCV/rv32-relaxation.s
  llvm/test/MC/RISCV/rv32c-only-valid.s
  llvm/test/MC/RISCV/rv32c-valid.s
  llvm/test/MC/RISCV/rv32e-valid.s
  llvm/test/MC/RISCV/rv32i-valid.s
  llvm/test/MC/RISCV/rv64-relax-all.s
  llvm/test/MC/RISCV/rv64-relaxation.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/utils/TableGen/AsmWriterEmitter.cpp
  llvm/utils/TableGen/AsmWriterInst.cpp
  llvm/utils/TableGen/CodeGenInstruction.cpp
  llvm/utils/TableGen/CodeGenInstruction.h

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