[PATCH] D80097: [PowerPC] add more high latency opcodes for machine combiner pass

[ChenZheng via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG8086cdd1b014: [PowerPC] add more high latency opcodes for machine combiner pass (authored by shchenz).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80097/new/

https://reviews.llvm.org/D80097

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/machine-combiner.ll


Index: llvm/test/CodeGen/PowerPC/machine-combiner.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/machine-combiner.ll
+++ llvm/test/CodeGen/PowerPC/machine-combiner.ll
@@ -189,9 +189,9 @@
 define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; FIXPOINT-LABEL: reassociate_mullw:
 ; FIXPOINT:       # %bb.0:
-; FIXPOINT:       mullw 3, 3, 4
-; FIXPOINT:       mullw 3, 3, 5
-; FIXPOINT:       mullw 3, 3, 6
+; FIXPOINT:       mullw [[REG0:[0-9]+]], 3, 4
+; FIXPOINT:       mullw [[REG1:[0-9]+]], 5, 6
+; FIXPOINT:       mullw 3, [[REG0]], [[REG1]]
 ; FIXPOINT-NEXT:  blr
 
   %t0 = mul i32 %x0, %x1
@@ -203,9 +203,9 @@
 define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; FIXPOINT-LABEL: reassociate_mulld:
 ; FIXPOINT:       # %bb.0:
-; FIXPOINT:       mulld 3, 3, 4
-; FIXPOINT:       mulld 3, 3, 5
-; FIXPOINT:       mulld 3, 3, 6
+; FIXPOINT:       mulld [[REG0:[0-9]+]], 3, 4
+; FIXPOINT:       mulld [[REG1:[0-9]+]], 5, 6
+; FIXPOINT:       mulld 3, [[REG0]], [[REG1]]
 ; FIXPOINT-NEXT:  blr
 
   %t0 = mul i64 %x0, %x1
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -235,10 +235,11 @@
 // This function does not list all associative and commutative operations, but
 // only those worth feeding through the machine combiner in an attempt to
 // reduce the critical path. Mostly, this means floating-point operations,
-// because they have high latencies (compared to other operations, such and
+// because they have high latencies(>=5) (compared to other operations, such as
 // and/or, which are also associative and commutative, but have low latencies).
 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   switch (Inst.getOpcode()) {
+  // Floating point:
   // FP Add:
   case PPC::FADD:
   case PPC::FADDS:
@@ -267,6 +268,13 @@
   case PPC::QVFMULSs:
     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
+  // Fixed point:
+  // Multiply:
+  case PPC::MULHD:
+  case PPC::MULLD:
+  case PPC::MULHW:
+  case PPC::MULLW:
+    return true;
   default:
     return false;
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D80097.265438.patch
Type: text/x-patch
Size: 2328 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200521/0de85ef4/attachment.bin>