[PATCH] D80120: [InstCombine] Sink pure instructions down to return and unreachable blocks

Wed May 20 23:58:57 PDT 2020

asbirlea added a comment.

In D80120#2048273 <https://reviews.llvm.org/D80120#2048273>, @mkazantsev wrote:

> In D80120#2048216 <https://reviews.llvm.org/D80120#2048216>, @asbirlea wrote:
>
> > FWIW, the added tests look good.
> >
> > I don't really see how the case of not sinking from A when A and B blocks merge in C can happen, if this applies for non-memory instructions only. But if it can, having a test for this would be good too.
>
>
> The only case where this may theoretically happen is shown in `test_05_neg`. The Phi in return block `bb3` initiates sinking from `bb0` to `bb2`, but it gets rejected  because bb2 has 2 preds. Another example of that (with non-phi instruction in ret block) is just not possible in SSA.

Right! I could not think of a case without a loop. Thank you for confirming!
This lgtm.  Leaving the final review to @jdoerfert.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80120/new/

https://reviews.llvm.org/D80120