[llvm] 8086cdd - [PowerPC] add more high latency opcodes for machine combiner pass

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2020-05-21T02:39:20-04:00
New Revision: 8086cdd1b014b2f35f0d3e3841c029c220712711

URL: https://github.com/llvm/llvm-project/commit/8086cdd1b014b2f35f0d3e3841c029c220712711
DIFF: https://github.com/llvm/llvm-project/commit/8086cdd1b014b2f35f0d3e3841c029c220712711.diff

LOG: [PowerPC] add more high latency opcodes for machine combiner pass

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D80097

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/test/CodeGen/PowerPC/machine-combiner.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index ad7e98af7495..1b98551e9cc9 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -235,10 +235,11 @@ void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &MI,
 // This function does not list all associative and commutative operations, but
 // only those worth feeding through the machine combiner in an attempt to
 // reduce the critical path. Mostly, this means floating-point operations,
-// because they have high latencies (compared to other operations, such and
+// because they have high latencies(>=5) (compared to other operations, such as
 // and/or, which are also associative and commutative, but have low latencies).
 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   switch (Inst.getOpcode()) {
+  // Floating point:
   // FP Add:
   case PPC::FADD:
   case PPC::FADDS:
@@ -267,6 +268,13 @@ bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   case PPC::QVFMULSs:
     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
+  // Fixed point:
+  // Multiply:
+  case PPC::MULHD:
+  case PPC::MULLD:
+  case PPC::MULHW:
+  case PPC::MULLW:
+    return true;
   default:
     return false;
   }

diff  --git a/llvm/test/CodeGen/PowerPC/machine-combiner.ll b/llvm/test/CodeGen/PowerPC/machine-combiner.ll
index 58bcdc2b9b42..7206d5e4dfaa 100644
--- a/llvm/test/CodeGen/PowerPC/machine-combiner.ll
+++ b/llvm/test/CodeGen/PowerPC/machine-combiner.ll
@@ -189,9 +189,9 @@ define double @reassociate_muls_double(double %x0, double %x1, double %x2, doubl
 define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; FIXPOINT-LABEL: reassociate_mullw:
 ; FIXPOINT:       # %bb.0:
-; FIXPOINT:       mullw 3, 3, 4
-; FIXPOINT:       mullw 3, 3, 5
-; FIXPOINT:       mullw 3, 3, 6
+; FIXPOINT:       mullw [[REG0:[0-9]+]], 3, 4
+; FIXPOINT:       mullw [[REG1:[0-9]+]], 5, 6
+; FIXPOINT:       mullw 3, [[REG0]], [[REG1]]
 ; FIXPOINT-NEXT:  blr
 
   %t0 = mul i32 %x0, %x1
@@ -203,9 +203,9 @@ define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; FIXPOINT-LABEL: reassociate_mulld:
 ; FIXPOINT:       # %bb.0:
-; FIXPOINT:       mulld 3, 3, 4
-; FIXPOINT:       mulld 3, 3, 5
-; FIXPOINT:       mulld 3, 3, 6
+; FIXPOINT:       mulld [[REG0:[0-9]+]], 3, 4
+; FIXPOINT:       mulld [[REG1:[0-9]+]], 5, 6
+; FIXPOINT:       mulld 3, [[REG0]], [[REG1]]
 ; FIXPOINT-NEXT:  blr
 
   %t0 = mul i64 %x0, %x1