[PATCH] D78494: [AMDGPU][CODEGEN] Added 'A' constraint for inline assembler

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:1429-1431
+  if ((Size == 16 && Val == 0x3118) ||
+      (Size == 32 && Val == 0x3e22f983))
+    return 0x3fc45f306dc9c882;
----------------
dp wrote:
> arsenm wrote:
> > Logic doesn't make sense here? Returns the 64-bit value if it's 16 or 32?
> When working on this fix I was under an impression that types of values passed to inline assembler are not required to match instruction operand types. In other words, I assumed that the following code is legal:
> 
> 
> ```
> "v_mov_b32 $0, $1", "=v,A"(half 0xH3C00) // 1.0h
> ```
> 
> Also I assumed that this code required a type conversion to end up as "v_mov_b32 ..., 1.0" and not "v_mov_b32 ..., 0x3C00" because in the latter case the constant cannot be encoded as inline value.
> 
> That assumption complicated implementation. Was the assumption incorrect?
> 
> If types of values passed to inline assembler are required to match types of corresponding assembler operands, the implementation would be much simpler.
> 
We have to use 32-bit instruction to materialize 16-bit values. This should be zero extended. This should end up as v_mov_b32 $0, 0x00003c00. For some cases we don't currently use in codegen, (and I'm not sure are supported by the assembler), some 64-bit operands accept 32-bit literals which are zero extended


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78494/new/

https://reviews.llvm.org/D78494