[PATCH] D80274: [MachineVerifier] Handle the PHI node for verifyLiveVariables()

Zhang Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 20 00:30:18 PDT 2020 

ZhangKang created this revision.
ZhangKang added reviewers: bjope, qcolombet, hfinkel, echristo, jonpa, PowerPC, mcrosier, dexonsmith, jnspaulsson, thegameg.
ZhangKang added a project: LLVM.
Herald added subscribers: luismarques, s.egerton, lenary, wuzish, PkmX, jfb, atanasyan, sunfish, simoncook, fedor.sergeev, aheejin, hiraditya, kristof.beyls, arichardson, tpr, aprantl, nemanjai, sdardis, jyknight, dschuff.
ZhangKang retitled this revision from "[MachineVerifier] Handle the PHI node for Live verifyLiveVariables()" to "[MachineVerifier] Handle the PHI node for verifyLiveVariables()".

When doing MachineVerifier for LiveVariables, the MachineVerifier pass will calculate the LiveVariables,
and compares the result with the result livevars pass gave. If they are different, verifyLiveVariables()
will give error.
But when we calculate the LiveVariables in MachineVerifier, we don't consider the PHI node, while livevars
considers, so we will get different result and verifyLiveVariables() will failed.
Now, we don't enable the verificatoin for LiveVariables, so we haven't get the failure for verifyLiveVariables().

In the function `MachineVerifier::checkLiveness()`, we don't handle the PHI node for LiveVariables check.

  // We don't know which virtual registers are live in, so only complain
  // if vreg was killed in this MBB. Otherwise keep track of vregs that
  // must be live in. PHI instructions are handled separately.
  if (MInfo.regsKilled.count(Reg))
    report("Using a killed virtual register", MO, MONum);
  else if (!MI->isPHI())
    MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));

But in `iveVariables.h`, we can see:

  /// PHI nodes complicate things a bit.  If a PHI node is the last user of a
  /// value in one of its predecessor blocks, it is not listed in the kills set,
  /// but does include the predecessor block in the AliveBlocks set (unless that
  /// block also defines the value).

It's obvious that, we should handle PHI in MachineVerifier, but we haven't.

For below case:

  48 body:             |
  49   bb.0.entry:
  50     successors: %bb.1(0x80000000)
  51     liveins: $x3
  52
  53     %4:g8rc_and_g8rc_nox0 = COPY killed $x3
  54     %0:g8rc = LD 0, %4 :: (dereferenceable load 8 from %ir.p)
  55
  56   bb.1.loop:
  57     successors: %bb.1(0x20000000), %bb.2(0x60000000)
  58
  59     %1:g8rc_and_g8rc_nox0 = PHI %0, %bb.0, %2, %bb.1, %3, %bb.3, %2, %bb.2
  60     %5:gprc = LBZ 0, %1 :: (load 1 from %ir.0)
  61     %6:crrc = CMPWI killed %5, 0
  62     %7:crbitrc = COPY killed %6.sub_eq
  63     %2:g8rc = nuw ADDI8 %1, 1
  64     STD %2, 0, %4 :: (store 8 into %ir.p)
  65     %8:gprc = LBZ 1, %1 :: (load 1 from %ir.incdec.ptr)
  66     BCn killed %7, %bb.1
  67     B %bb.2
  68
  69   bb.2.loop:
  70     successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab)
  71
  72     %9:crrc = CMPWI killed %8, 0
  73     %10:crbitrc = COPY killed %9.sub_eq
  74     BC killed %10, %bb.1
  75     B %bb.3
  76
  77   bb.3.if.then3:
  78     successors: %bb.1(0x80000000)
  79
  80     %3:g8rc = nuw ADDI8 killed %1, 2
  81     STD %3, 0, %4 :: (store 8 into %ir.p)
  82     B %bb.1

We will get below error:

  # Bad machine code: LiveVariables: Block should not be in AliveBlocks
  # - function:    zext_free
  # - basic block: %bb.2 loop
  # Virtual register %2 is not needed live through the block.
  # LLVM ERROR: Found 1 machine code errors.

But in fact, %2 is should live through the %bb.2. In the line 59 for PHI, %2 can be 
from %bb.1 or %bb.2, and %2 is defined in %bb.1, so %2 is live through %bb2, not live 
through %bb1.

Below is the liveVariables info for above case:

  Reg: %1  Alive in blocks: 2,
    Killed by:
      #0: %3:g8rc = nuw ADDI8 killed %1:g8rc_and_g8rc_nox0, 2
  
  Reg: %2  Alive in blocks: 2,
    Killed by: No instructions.
  
  Reg: %4  Alive in blocks: 1, 2, 3,
    Killed by: No instructions.

This patch can fix 210 verification error for LiveVariables, if you need test it, you should enable all pass verification and enable EXPENSIVE_CHECKS.

  LLVM :: CodeGen/AArch64/arm64-ccmp-heuristics.ll
  LLVM :: CodeGen/AArch64/arm64-fp128.ll
  LLVM :: CodeGen/AArch64/arm64-jumptable.ll
  LLVM :: CodeGen/AArch64/arm64-regress-f128csel-flags.ll
  LLVM :: CodeGen/AArch64/atomic-ops-not-barriers.ll
  LLVM :: CodeGen/AArch64/br-undef-cond.ll
  LLVM :: CodeGen/AArch64/fast-isel-switch-phi.ll
  LLVM :: CodeGen/AArch64/ifcvt-select.ll
  LLVM :: CodeGen/AArch64/pr27816.ll
  LLVM :: CodeGen/AArch64/regress-f128csel-flags.ll
  LLVM :: CodeGen/AArch64/taildup-cfi.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/lds-size.ll
  LLVM :: CodeGen/AMDGPU/add-debug.ll
  LLVM :: CodeGen/AMDGPU/add.ll
  LLVM :: CodeGen/AMDGPU/coalescer_remat.ll
  LLVM :: CodeGen/AMDGPU/collapse-endcf.ll
  LLVM :: CodeGen/AMDGPU/cse-phi-incoming-val.ll
  LLVM :: CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
  LLVM :: CodeGen/AMDGPU/global_smrd_cfg.ll
  LLVM :: CodeGen/AMDGPU/i1-copy-from-loop.ll
  LLVM :: CodeGen/AMDGPU/infinite-loop.ll
  LLVM :: CodeGen/AMDGPU/llvm.amdgcn.softwqm.ll
  LLVM :: CodeGen/AMDGPU/loop_break.ll
  LLVM :: CodeGen/AMDGPU/mad_int24.ll
  LLVM :: CodeGen/AMDGPU/mfma-loop.ll
  LLVM :: CodeGen/AMDGPU/mul.ll
  LLVM :: CodeGen/AMDGPU/mul24-pass-ordering.ll
  LLVM :: CodeGen/AMDGPU/multi-divergent-exit-region.ll
  LLVM :: CodeGen/AMDGPU/multilevel-break.ll
  LLVM :: CodeGen/AMDGPU/promote-constOffset-to-imm.ll
  LLVM :: CodeGen/AMDGPU/sgprcopies.ll
  LLVM :: CodeGen/AMDGPU/si-annotate-cf.ll
  LLVM :: CodeGen/AMDGPU/si-lower-control-flow-kill.ll
  LLVM :: CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
  LLVM :: CodeGen/AMDGPU/valu-i1.ll
  LLVM :: CodeGen/AMDGPU/xor.ll
  LLVM :: CodeGen/ARM/2009-02-27-SpillerBug.ll
  LLVM :: CodeGen/ARM/2009-05-11-CodePlacementCrash.ll
  LLVM :: CodeGen/ARM/2011-08-25-ldmia_ret.ll
  LLVM :: CodeGen/ARM/analyze-branch-bkpt.ll
  LLVM :: CodeGen/ARM/arm-negative-stride.ll
  LLVM :: CodeGen/ARM/code-placement.ll
  LLVM :: CodeGen/ARM/debug-frame-vararg.ll
  LLVM :: CodeGen/ARM/debug-info-sreg2.ll
  LLVM :: CodeGen/ARM/ifcvt11.ll
  LLVM :: CodeGen/ARM/ifcvt4.ll
  LLVM :: CodeGen/ARM/lsr-code-insertion.ll
  LLVM :: CodeGen/ARM/tail-dup-kill-flags.ll
  LLVM :: CodeGen/Generic/select-cc.ll
  LLVM :: CodeGen/Generic/undef-phi.ll
  LLVM :: CodeGen/Hexagon/P08214.ll
  LLVM :: CodeGen/Hexagon/aggressive_licm.ll
  LLVM :: CodeGen/Hexagon/autohvx/isel-shift-byte.ll
  LLVM :: CodeGen/Hexagon/bit-loop-rc-mismatch.ll
  LLVM :: CodeGen/Hexagon/blockaddr-fpic.ll
  LLVM :: CodeGen/Hexagon/brcond-setne.ll
  LLVM :: CodeGen/Hexagon/bug14859-iv-cleanup-lpad.ll
  LLVM :: CodeGen/Hexagon/bug17276.ll
  LLVM :: CodeGen/Hexagon/constext-immstore.ll
  LLVM :: CodeGen/Hexagon/constext-replace.ll
  LLVM :: CodeGen/Hexagon/deflate.ll
  LLVM :: CodeGen/Hexagon/early-if-merge-loop.ll
  LLVM :: CodeGen/Hexagon/early-if-spare.ll
  LLVM :: CodeGen/Hexagon/eh_save_restore.ll
  LLVM :: CodeGen/Hexagon/entryBB-isLoopHdr.ll
  LLVM :: CodeGen/Hexagon/expand-condsets-undefvni.ll
  LLVM :: CodeGen/Hexagon/expand-condsets.ll
  LLVM :: CodeGen/Hexagon/find-loop.ll
  LLVM :: CodeGen/Hexagon/fixed-spill-mutable.ll
  LLVM :: CodeGen/Hexagon/honor-optsize.ll
  LLVM :: CodeGen/Hexagon/hwloop-long.ll
  LLVM :: CodeGen/Hexagon/hwloop-pos-ivbump1.ll
  LLVM :: CodeGen/Hexagon/hwloop-preheader.ll
  LLVM :: CodeGen/Hexagon/hwloop-recursion.ll
  LLVM :: CodeGen/Hexagon/jump-prob.ll
  LLVM :: CodeGen/Hexagon/jump-table-isel.ll
  LLVM :: CodeGen/Hexagon/loop-rotate-bug.ll
  LLVM :: CodeGen/Hexagon/memcmp.ll
  LLVM :: CodeGen/Hexagon/opt-addr-mode.ll
  LLVM :: CodeGen/Hexagon/opt-glob-addrs-003.ll
  LLVM :: CodeGen/Hexagon/packetize-impdef-1.ll
  LLVM :: CodeGen/Hexagon/pred-simp.ll
  LLVM :: CodeGen/Hexagon/rdf-copy.ll
  LLVM :: CodeGen/Hexagon/rdf-phi-up.ll
  LLVM :: CodeGen/Hexagon/sdr-nosplit1.ll
  LLVM :: CodeGen/Hexagon/sub-add.ll
  LLVM :: CodeGen/Hexagon/swp-kernel-phi1.ll
  LLVM :: CodeGen/Hexagon/swp-loop-carried-crash.ll
  LLVM :: CodeGen/Hexagon/swp-loop-carried-unknown.ll
  LLVM :: CodeGen/Hexagon/swp-multi-phi-refs.ll
  LLVM :: CodeGen/Hexagon/swp-order-deps6.ll
  LLVM :: CodeGen/Hexagon/swp-regseq.ll
  LLVM :: CodeGen/Hexagon/vararg-linux-abi.ll
  LLVM :: CodeGen/Hexagon/vassign-to-combine.ll
  LLVM :: CodeGen/Hexagon/vect/vect-shuffle.ll
  LLVM :: CodeGen/Hexagon/vect/vect-xor.ll
  LLVM :: CodeGen/Mips/addressing-mode.ll
  LLVM :: CodeGen/Mips/brundef.ll
  LLVM :: CodeGen/Mips/call-optimization.ll
  LLVM :: CodeGen/Mips/lazy-binding.ll
  LLVM :: CodeGen/Mips/mips3-spill-slot.ll
  LLVM :: CodeGen/Mips/selpat.ll
  LLVM :: CodeGen/PowerPC/2007-11-16-landingpad-split.ll
  LLVM :: CodeGen/PowerPC/2008-07-15-Fabs.ll
  LLVM :: CodeGen/PowerPC/2008-10-28-f128-i32.ll
  LLVM :: CodeGen/PowerPC/PR3488.ll
  LLVM :: CodeGen/PowerPC/branch-opt.ll
  LLVM :: CodeGen/PowerPC/branch_coalesce.ll
  LLVM :: CodeGen/PowerPC/change-no-infs.ll
  LLVM :: CodeGen/PowerPC/cr1eq-no-extra-moves.ll
  LLVM :: CodeGen/PowerPC/ctrloop-large-ec.ll
  LLVM :: CodeGen/PowerPC/ctrloop-reg.ll
  LLVM :: CodeGen/PowerPC/expand-contiguous-isel.ll
  LLVM :: CodeGen/PowerPC/f128-compare.ll
  LLVM :: CodeGen/PowerPC/fsel.ll
  LLVM :: CodeGen/PowerPC/int-fp-conv-0.ll
  LLVM :: CodeGen/PowerPC/knowCRBitSpill.ll
  LLVM :: CodeGen/PowerPC/licm-tocReg.ll
  LLVM :: CodeGen/PowerPC/loop-hoist-toc-save.ll
  LLVM :: CodeGen/PowerPC/lsr-postinc-pos.ll
  LLVM :: CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll
  LLVM :: CodeGen/PowerPC/no-duplicate.ll
  LLVM :: CodeGen/PowerPC/pow.75.ll
  LLVM :: CodeGen/PowerPC/ppcf128-4.ll
  LLVM :: CodeGen/PowerPC/pr26690.ll
  LLVM :: CodeGen/PowerPC/pr42492.ll
  LLVM :: CodeGen/PowerPC/preincprep-i64-check.ll
  LLVM :: CodeGen/PowerPC/scalar-equal.ll
  LLVM :: CodeGen/PowerPC/scalar-min-max.ll
  LLVM :: CodeGen/PowerPC/scalar_cmp.ll
  LLVM :: CodeGen/PowerPC/select-i1-vs-i1.ll
  LLVM :: CodeGen/PowerPC/spe.ll
  LLVM :: CodeGen/PowerPC/tocSaveInPrologue.ll
  LLVM :: CodeGen/PowerPC/uint-to-ppcfp128-crash.ll
  LLVM :: CodeGen/PowerPC/vec-min-max.ll
  LLVM :: CodeGen/PowerPC/vec_select.ll
  LLVM :: CodeGen/PowerPC/zext-free.ll
  LLVM :: CodeGen/RISCV/addcarry.ll
  LLVM :: CodeGen/RISCV/alu64.ll
  LLVM :: CodeGen/RISCV/atomic-rmw.ll
  LLVM :: CodeGen/RISCV/bare-select.ll
  LLVM :: CodeGen/RISCV/compress.ll
  LLVM :: CodeGen/RISCV/double-select-fcmp.ll
  LLVM :: CodeGen/RISCV/float-select-fcmp.ll
  LLVM :: CodeGen/RISCV/remat.ll
  LLVM :: CodeGen/RISCV/select-cc.ll
  LLVM :: CodeGen/RISCV/select-optimize-multiple.ll
  LLVM :: CodeGen/RISCV/shifts.ll
  LLVM :: CodeGen/SPARC/varargs.ll
  LLVM :: CodeGen/SystemZ/fp-cmp-03.ll
  LLVM :: CodeGen/SystemZ/fp-cmp-05.ll
  LLVM :: CodeGen/SystemZ/fp-libcall.ll
  LLVM :: CodeGen/SystemZ/fp-strict-cmp-03.ll
  LLVM :: CodeGen/SystemZ/fp-strict-cmp-05.ll
  LLVM :: CodeGen/SystemZ/fp-strict-cmps-03.ll
  LLVM :: CodeGen/SystemZ/fp-strict-cmps-05.ll
  LLVM :: CodeGen/SystemZ/int-cmp-16.ll
  LLVM :: CodeGen/SystemZ/int-cmp-17.ll
  LLVM :: CodeGen/SystemZ/int-cmp-18.ll
  LLVM :: CodeGen/SystemZ/int-cmp-19.ll
  LLVM :: CodeGen/SystemZ/int-cmp-20.ll
  LLVM :: CodeGen/SystemZ/int-cmp-21.ll
  LLVM :: CodeGen/SystemZ/int-cmp-24.ll
  LLVM :: CodeGen/SystemZ/int-cmp-25.ll
  LLVM :: CodeGen/SystemZ/int-cmp-26.ll
  LLVM :: CodeGen/SystemZ/int-cmp-27.ll
  LLVM :: CodeGen/SystemZ/int-cmp-28.ll
  LLVM :: CodeGen/SystemZ/int-cmp-29.ll
  LLVM :: CodeGen/SystemZ/int-cmp-30.ll
  LLVM :: CodeGen/SystemZ/int-cmp-31.ll
  LLVM :: CodeGen/SystemZ/int-cmp-55.ll
  LLVM :: CodeGen/SystemZ/spill-01.ll
  LLVM :: CodeGen/Thumb/2010-07-15-debugOrdering.ll
  LLVM :: CodeGen/Thumb/large-fn-switch.ll
  LLVM :: CodeGen/Thumb/ragreedy-implicit-def.ll
  LLVM :: CodeGen/Thumb/select.ll
  LLVM :: CodeGen/Thumb/thumb-shrink-wrapping.ll
  LLVM :: CodeGen/Thumb2/2009-08-04-ScavengerAssert.ll
  LLVM :: CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
  LLVM :: CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
  LLVM :: CodeGen/Thumb2/constant-hoisting.ll
  LLVM :: CodeGen/Thumb2/ifcvt-no-branch-predictor.ll
  LLVM :: CodeGen/Thumb2/thumb2-ifcvt1.ll
  LLVM :: CodeGen/WebAssembly/cfg-stackify.ll
  LLVM :: CodeGen/WebAssembly/dead-vreg.ll
  LLVM :: CodeGen/WebAssembly/lower-em-sjlj-sret.ll
  LLVM :: CodeGen/WebAssembly/mem-intrinsics.ll
  LLVM :: CodeGen/WebAssembly/reg-stackify.ll
  LLVM :: CodeGen/WebAssembly/userstack.ll
  LLVM :: CodeGen/X86/2004-10-08-SelectSetCCFold.ll
  LLVM :: CodeGen/X86/2008-05-21-CoalescerBug.ll
  LLVM :: CodeGen/X86/2010-02-23-SingleDefPhiJoin.ll
  LLVM :: CodeGen/X86/GlobalISel/phi.ll
  LLVM :: CodeGen/X86/fp-stack-compare.ll
  LLVM :: CodeGen/X86/legalize-fmp-oeq-vector-select.ll
  LLVM :: CodeGen/X86/merge-sp-update-lea.ll
  LLVM :: CodeGen/X86/tail-dup-catchret.ll
  LLVM :: CodeGen/X86/win-catchpad-varargs.ll
  LLVM :: DebugInfo/ARM/s-super-register.ll
  LLVM :: DebugInfo/WebAssembly/dbg-value-dwarfdump.ll
  LLVM :: DebugInfo/WebAssembly/dbg-value-live-interval.ll
  LLVM :: DebugInfo/WebAssembly/dbg-value-move-2.ll
  LLVM :: DebugInfo/WebAssembly/dbg-value-move.ll
  LLVM :: DebugInfo/WebAssembly/dbg-value-ti.ll
  LLVM :: MC/ARM/data-in-code.ll
  LLVM :: Transforms/CodeGenPrepare/ARM/large-offset-gep.ll
  LLVM :: Transforms/LoopStrengthReduce/AArch64/req-regs.ll
  LLVM :: Transforms/LoopStrengthReduce/AArch64/small-constant.ll
  LLVM :: Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80274

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/CodeGen/PowerPC/livevars-crash1.mir
  llvm/test/CodeGen/PowerPC/livevars-crash2.mir
  llvm/test/MachineVerifier/test_phis_precede_nonphis.mir

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