[llvm] 3c84353 - [AMDGPU] Add the test from D49097.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-05-20T14:34:51+01:00
New Revision: 3c843538048e6439426a555698917051c1f3f3e1

URL: https://github.com/llvm/llvm-project/commit/3c843538048e6439426a555698917051c1f3f3e1
DIFF: https://github.com/llvm/llvm-project/commit/3c843538048e6439426a555698917051c1f3f3e1.diff

LOG: [AMDGPU] Add the test from D49097.

Added: 
    llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
new file mode 100644
index 000000000000..c87b1f3459d3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/coalescing-subreg-was-undef-but-became-def.mir
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+#
+# This is another example of a test giving "Couldn't join subrange!"
+#
+# This shows a case where a whole reg use point of the whole register was
+# undefined in one subreg, but after coalescing it became defined but the
+# subrange was not updated to reflect that.
+#
+
+---
+name: coalescing_makes_lane_defined
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: coalescing_makes_lane_defined
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   undef %4.sub2:sgpr_128 = S_MOV_B32 0
+  ; CHECK:   dead undef %7.sub0:sgpr_128 = S_MOV_B32 0
+  ; CHECK:   S_CBRANCH_SCC0 %bb.2, implicit undef $scc
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   %4.sub0:sgpr_128 = S_MOV_B32 -1
+  ; CHECK: bb.2:
+  ; CHECK:   S_NOP 0, implicit %4
+  bb.0:
+    successors: %bb.1, %bb.2
+
+    %0:sreg_32_xm0 = S_MOV_B32 0
+    undef %1.sub2:sgpr_128 = COPY %0
+    undef %2.sub0:sgpr_128 = S_MOV_B32 0
+    undef %3.sub2:sgpr_128 = COPY %0
+    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
+
+  bb.1:
+    successors: %bb.2
+
+    undef %4.sub0:sgpr_128 = S_MOV_B32 -1
+    %4.sub2:sgpr_128 = COPY killed %0
+    %5:sgpr_128 = COPY killed %4
+    %6:sgpr_128 = COPY killed %1
+    %3:sgpr_128 = COPY killed %6
+    %2:sgpr_128 = COPY killed %5
+
+  bb.2:
+    S_NOP 0, implicit killed %3
+
+...