[PATCH] D78494: [AMDGPU][CODEGEN] Added 'A' constraint for inline assembler

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:10735
+    } else if (BuildVectorSDNode *V = dyn_cast<BuildVectorSDNode>(Op)) {
+      if (Size != 16 || Op.getNumOperands() != 2)
+        return;
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dp wrote:
> Should we enforce this limitation? GCC seems to allow arbitrary vector size and type provided that all elements are equal and may be inlined.
You mean it also accepts <4 x i8> because it's a 32-bit type?


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Comment at: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:1429-1431
+  if ((Size == 16 && Val == 0x3118) ||
+      (Size == 32 && Val == 0x3e22f983))
+    return 0x3fc45f306dc9c882;
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Logic doesn't make sense here? Returns the 64-bit value if it's 16 or 32?


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Comment at: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:1434-1443
+  if (Size < 64) {
+    bool Lost;
+    const fltSemantics *FltSemantics =
+      (Size == 16) ? &APFloat::IEEEhalf() : &APFloat::IEEEsingle();
+    APFloat FPLiteral(*FltSemantics, APInt(Size, Val));
+    FPLiteral.convert(APFloat::IEEEdouble(),
+                      APFloat::rmNearestTiesToEven,
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I wouldn't expect any FP rounding in the assembler


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78494/new/

https://reviews.llvm.org/D78494