[PATCH] D80201: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86SchedBroadwell.td:243
+defm : X86WriteRes<WriteVecMaskedStore64,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
+defm : X86WriteRes<WriteVecMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 
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TBH it's better if we can keep the integer vector entries all together, not put in the float vector sections - same for all other models


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https://reviews.llvm.org/D80201