[PATCH] D80201: [X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975). NFC

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, lebedev.ri, craig.topper.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
andreadb updated this revision to Diff 264841.
andreadb added a comment.

Patch updated. This time with context.


This effectively splits the scheduling WriteVecMaskedStore(Y) classes
into four different classes (one per each variant).

VecMaskedStores are now correctly marked as 'unsupported' by the bdver2
and btver2 models (since those are only used for AVX2 VPMASKMOV variants).

No functional change intended.


https://reviews.llvm.org/D80201

Files:
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/lib/Target/X86/X86Schedule.td
  llvm/lib/Target/X86/X86ScheduleAtom.td
  llvm/lib/Target/X86/X86ScheduleBdVer2.td
  llvm/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/lib/Target/X86/X86ScheduleSLM.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86ScheduleZnver2.td

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