[PATCH] D80196: MIR Statepoint refactoring: pass GC pointers in VRegs. Part 5/5.

[Denis Antrushin via Phabricator via llvm-commits]

dantrushin created this revision.
dantrushin added reviewers: reames, skatkov.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

Change MIR representation of STATEPOINT instruction from explicit
spill/reload of GC pointer arguments around statepoint to simply
assigning them to virtual registers. Then they can be spilled as
necessary. Relocated pointers are represented as STATEPOINT's Def
operands (tied to corresponding derived pointers from GC args list):

  rel1,rel2,... = STATEPOINT ..., derived1<tied-def0>, derived2<tied-def1>, ...

This patch enhances FixupStatepointCallerSaved pass with ability to
spill/reload GC pointers passed in registers, optionally allowing
them to stay in CSRs.

Depends On: D80195 <https://reviews.llvm.org/D80195>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80196

Files:
  llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
  llvm/test/CodeGen/X86/statepoint-call-lowering.ll
  llvm/test/CodeGen/X86/statepoint-duplicates-export.ll
  llvm/test/CodeGen/X86/statepoint-invoke.ll
  llvm/test/CodeGen/X86/statepoint-no-extra-const.ll
  llvm/test/CodeGen/X86/statepoint-regs.ll
  llvm/test/CodeGen/X86/statepoint-uniqueing.ll

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