[PATCH] D80193: MIR Statepoint refactoring: pass GC pointers in VRegs. Part 3/5.

[Denis Antrushin via Phabricator via llvm-commits]

dantrushin created this revision.
dantrushin added reviewers: reames, skatkov, bogner.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

Change MIR representation of STATEPOINT instruction from explicit
spill/reload of GC pointer arguments around statepoint to simply
assigning them to virtual registers. Then they can be spilled as
necessary. Relocated pointers are represented as STATEPOINT's Def
operands (tied to corresponding derived pointers from GC args list):

rel1,rel2,... = STATEPOINT ..., derived1<tied-def0>, derived2<tied-def1>, ...

This patch implements actual lowering with new statepoint representation.
Due to storage limitation of SDNode, first `N` base and derived pointers
pairs from GC Args list are assigned to virtual registers (of course,
only those which need relocations for derived pointers).
Upper value of `N` is bounded by the maximal amount of tied registers
MachineInstr can manage (currently, 15). The rest, if any, is passed
on stack slots, as in the old implementation.

Depends On: D80192 <https://reviews.llvm.org/D80192>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80193

Files:
  llvm/include/llvm/CodeGen/FunctionLoweringInfo.h
  llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
  llvm/lib/CodeGen/TargetLoweringBase.cpp

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