[PATCH] D78910: [RISCV] RISCBoy Scheduling Model
Sam Elliott via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 18 10:48:16 PDT 2020
lenary planned changes to this revision.
lenary added a comment.
I still need to implement Forwarding, `LoopMicroOpBufferSize` should definitely be zero, and the whole model should refer to the Core, which is now officially called Hazard5 (and is being used in more projects).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78910/new/
https://reviews.llvm.org/D78910
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