[PATCH] D80139: [CodeGen][SVE] CopyToReg: Split scalable EVTs that are not powers of 2

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen marked 2 inline comments as done.
sdesmalen added inline comments.


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Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:955
+  if (VT.isScalableVector() && !isPowerOf2_32(EC.Min))
+    llvm_unreachable(
+        "Splitting or widening of non-power-of-2 MVTs is not implemented.");
----------------
The reason for not implementing this yet is because I don't have a way to test it.


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Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:1425
+  // Scalable vectors cannot be scalarized, so splitting is required.
+  // FIXME: Implement widening of scalable vectors.
+  if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.Min)) {
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note: Widening of scalable vectors requires a bit more thought.

For example, I wasn't sure how a `<vscale x 3 x i8>` should be widened at this level. Is it widened to a `<vscale x 4 x i8>` and then promoted to a `<vscale x 4 x i32>`, or do we keep it simple and always insert it into an UNDEF of the first legal type (`<vscale x 16 x i8>` for SVE).

It would also require changes to legalise e.g. `<vscale x 9 x i16>`, that needs both widening to `<vscale x 16 x i16>`, and then splitting to two `<vscale x 8 x i16>`.

The case handled by this patch allows it to support the tuple types for the structured load/store instructions, such as svint32x3_t (implemented as `<vscale x 12 x i32>`).



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  https://reviews.llvm.org/D80139/new/

https://reviews.llvm.org/D80139