[PATCH] D77316: [AArch64] Add a special case for shifting by (BitWidth - 1) - X
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat May 16 11:05:38 PDT 2020
efriedma added a comment.
What happens if the shift amount has more than one use?
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2794
+ MachineSDNode *Not =
+ CurDAG->getMachineNode(NotOpc, DL, SubVT, Add1, Zero);
+ NewShiftAmt = SDValue(Not, 0);
----------------
Please use mvn to NOT a register. (This doesn't affect performance, but it's more readable.)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77316/new/
https://reviews.llvm.org/D77316
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