[PATCH] D80044: AllocaInst should store Align instead of MaybeAlign.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
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efriedma marked 2 inline comments as done.
efriedma added inline comments.


================
Comment at: llvm/lib/AsmParser/LLParser.cpp:7071
+  SmallPtrSet<Type *, 4> Visited;
+  if (!Alignment && !Ty->isSized(&Visited))
     return Error(ExplicitTypeLoc, "loading unsized types is not allowed");
----------------
I guess it's worth briefly noting what this is about: if isSized is passed a SmallPtrSet, it uses that set to catch infinitely recursive types (for example, a struct that has itself as a member).  Otherwise, it just crashes on such types.

An existing test for alloca caught this, so while I was here I extended the same check to load/store.


================
Comment at: llvm/lib/Transforms/IPO/ArgumentPromotion.cpp:390
+          AgTy, DL.getAllocaAddrSpace(), nullptr,
+          I->getParamAlign().getValueOr(DL.getPrefTypeAlign(AgTy)), "",
+          InsertPt);
----------------
I'm not completely confident this is correct; LangRef says the default alignment of a byval argument is target-dependent (not encoded in the datalayout), so it could theoretically by higher than getPrefTypeAlign().  But this matches the current behavior of the code.


Along the lines of D77454 <https://reviews.llvm.org/D77454> and D79968 <https://reviews.llvm.org/D79968>.  Unlike loads and stores, the default alignment is getPrefTypeAlign, to match the existing handling in various places, including SelectionDAG and InstCombine.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D80044

Files:
  llvm/include/llvm/IR/Instructions.h
  llvm/include/llvm/Transforms/Scalar/MemCpyOptimizer.h
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/Bitcode/Reader/BitcodeReader.cpp
  llvm/lib/CodeGen/CodeGenPrepare.cpp
  llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/IR/Core.cpp
  llvm/lib/IR/Instructions.cpp
  llvm/lib/Target/AArch64/AArch64StackTagging.cpp
  llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
  llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
  llvm/lib/Transforms/Coroutines/CoroElide.cpp
  llvm/lib/Transforms/Coroutines/CoroFrame.cpp
  llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
  llvm/lib/Transforms/IPO/AttributorAttributes.cpp
  llvm/lib/Transforms/IPO/Inliner.cpp
  llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
  llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
  llvm/lib/Transforms/Scalar/GVNHoist.cpp
  llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
  llvm/lib/Transforms/Scalar/SROA.cpp
  llvm/lib/Transforms/Utils/Local.cpp
  llvm/test/Assembler/alloca-addrspace-elems.ll
  llvm/test/Assembler/alloca-addrspace0.ll
  llvm/test/Assembler/block-labels.ll
  llvm/test/Assembler/datalayout-alloca-addrspace-mismatch-0.ll
  llvm/test/Assembler/datalayout-alloca-addrspace.ll
  llvm/test/Assembler/drop-debug-info-nonzero-alloca.ll
  llvm/test/CodeGen/AMDGPU/alloca.ll
  llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
  llvm/test/Transforms/ArgumentPromotion/attrs.ll
  llvm/test/Transforms/ArgumentPromotion/byval-2.ll
  llvm/test/Transforms/ArgumentPromotion/byval.ll
  llvm/test/Transforms/ArgumentPromotion/dbg.ll
  llvm/test/Transforms/ArgumentPromotion/tail.ll
  llvm/test/Transforms/Attributor/ArgumentPromotion/attrs.ll
  llvm/test/Transforms/Attributor/ArgumentPromotion/byval-2.ll
  llvm/test/Transforms/Attributor/ArgumentPromotion/byval.ll
  llvm/test/Transforms/Attributor/ArgumentPromotion/fp80.ll
  llvm/test/Transforms/Attributor/ArgumentPromotion/inalloca.ll
  llvm/test/Transforms/Attributor/ArgumentPromotion/tail.ll
  llvm/test/Transforms/Attributor/IPConstantProp/2009-09-24-byval-ptr.ll
  llvm/test/Transforms/Attributor/value-simplify.ll
  llvm/test/Transforms/NewGVN/pr33367.ll
  llvm/test/Transforms/SROA/alignment.ll
  llvm/test/Transforms/SROA/pointer-offset-size.ll
  mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
  polly/lib/CodeGen/BlockGenerators.cpp
  polly/lib/CodeGen/IslNodeBuilder.cpp

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