[llvm] 245679b - [SVE] Remove usages of VectorType::getNumElements() from ARM
Christopher Tetreault via llvm-commits
llvm-commits at lists.llvm.org
Fri May 15 12:56:35 PDT 2020
Author: Christopher Tetreault
Date: 2020-05-15T12:55:27-07:00
New Revision: 245679b62ea90eeeb36521f575073ec7fdf56b45
URL: https://github.com/llvm/llvm-project/commit/245679b62ea90eeeb36521f575073ec7fdf56b45
DIFF: https://github.com/llvm/llvm-project/commit/245679b62ea90eeeb36521f575073ec7fdf56b45.diff
LOG: [SVE] Remove usages of VectorType::getNumElements() from ARM
Reviewers: efriedma, fpetrogalli, kmclaughlin, grosbach, dmgreen
Reviewed By: dmgreen
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, dmgreen, danielkiss, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D79816
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
llvm/lib/Target/ARM/MVETailPredication.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 80336f7d41ad..85076b299476 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -17878,7 +17878,7 @@ ARMTargetLowering::getNumInterleavedAccesses(VectorType *VecTy,
}
bool ARMTargetLowering::isLegalInterleavedAccessType(
- unsigned Factor, VectorType *VecTy, const DataLayout &DL) const {
+ unsigned Factor, FixedVectorType *VecTy, const DataLayout &DL) const {
unsigned VecSize = DL.getTypeSizeInBits(VecTy);
unsigned ElSize = DL.getTypeSizeInBits(VecTy->getElementType());
@@ -17937,7 +17937,7 @@ bool ARMTargetLowering::lowerInterleavedLoad(
assert(Shuffles.size() == Indices.size() &&
"Unmatched number of shufflevectors and indices");
- VectorType *VecTy = Shuffles[0]->getType();
+ auto *VecTy = cast<FixedVectorType>(Shuffles[0]->getType());
Type *EltTy = VecTy->getElementType();
const DataLayout &DL = LI->getModule()->getDataLayout();
@@ -17953,7 +17953,7 @@ bool ARMTargetLowering::lowerInterleavedLoad(
// A pointer vector can not be the return type of the ldN intrinsics. Need to
// load integer vectors first and then convert to pointer vectors.
if (EltTy->isPointerTy())
- VecTy = VectorType::get(DL.getIntPtrType(EltTy), VecTy->getNumElements());
+ VecTy = FixedVectorType::get(DL.getIntPtrType(EltTy), VecTy);
IRBuilder<> Builder(LI);
@@ -17963,8 +17963,8 @@ bool ARMTargetLowering::lowerInterleavedLoad(
if (NumLoads > 1) {
// If we're going to generate more than one load, reset the sub-vector type
// to something legal.
- VecTy = VectorType::get(VecTy->getElementType(),
- VecTy->getNumElements() / NumLoads);
+ VecTy = FixedVectorType::get(VecTy->getElementType(),
+ VecTy->getNumElements() / NumLoads);
// We will compute the pointer operand of each load from the original base
// address using GEPs. Cast the base address to a pointer to the scalar
@@ -18033,8 +18033,8 @@ bool ARMTargetLowering::lowerInterleavedLoad(
// Convert the integer vector to pointer vector if the element is pointer.
if (EltTy->isPointerTy())
SubVec = Builder.CreateIntToPtr(
- SubVec, VectorType::get(SV->getType()->getElementType(),
- VecTy->getNumElements()));
+ SubVec,
+ FixedVectorType::get(SV->getType()->getElementType(), VecTy));
SubVecs[SV].push_back(SubVec);
}
@@ -18086,12 +18086,12 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
"Invalid interleave factor");
- VectorType *VecTy = SVI->getType();
+ auto *VecTy = cast<FixedVectorType>(SVI->getType());
assert(VecTy->getNumElements() % Factor == 0 && "Invalid interleaved store");
unsigned LaneLen = VecTy->getNumElements() / Factor;
Type *EltTy = VecTy->getElementType();
- VectorType *SubVecTy = VectorType::get(EltTy, LaneLen);
+ auto *SubVecTy = FixedVectorType::get(EltTy, LaneLen);
const DataLayout &DL = SI->getModule()->getDataLayout();
@@ -18113,12 +18113,12 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
Type *IntTy = DL.getIntPtrType(EltTy);
// Convert to the corresponding integer vector.
- Type *IntVecTy = VectorType::get(
- IntTy, cast<VectorType>(Op0->getType())->getNumElements());
+ auto *IntVecTy =
+ FixedVectorType::get(IntTy, cast<FixedVectorType>(Op0->getType()));
Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
- SubVecTy = VectorType::get(IntTy, LaneLen);
+ SubVecTy = FixedVectorType::get(IntTy, LaneLen);
}
// The base address of the store.
@@ -18128,7 +18128,7 @@ bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
// If we're going to generate more than one store, reset the lane length
// and sub-vector type to something legal.
LaneLen /= NumStores;
- SubVecTy = VectorType::get(SubVecTy->getElementType(), LaneLen);
+ SubVecTy = FixedVectorType::get(SubVecTy->getElementType(), LaneLen);
// We will compute the pointer operand of each store from the original base
// address using GEPs. Cast the base address to a pointer to the scalar
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index c5f7183684f6..0f9aeb13384b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -643,7 +643,7 @@ class VectorType;
/// Returns true if \p VecTy is a legal interleaved access type. This
/// function checks the vector element type and the overall width of the
/// vector.
- bool isLegalInterleavedAccessType(unsigned Factor, VectorType *VecTy,
+ bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy,
const DataLayout &DL) const;
bool alignLoopsWithOptSize() const override;
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index 3864e2894172..9a55f58e14c9 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -491,7 +491,7 @@ int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
// result anyway.
return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index),
ST->getMVEVectorCostFactor()) *
- cast<VectorType>(ValTy)->getNumElements() / 2;
+ cast<FixedVectorType>(ValTy)->getNumElements() / 2;
}
return BaseT::getVectorInstrCost(Opcode, ValTy, Index);
@@ -572,7 +572,7 @@ bool ARMTTIImpl::isLegalMaskedLoad(Type *DataTy, MaybeAlign Alignment) {
if (!EnableMaskedLoadStores || !ST->hasMVEIntegerOps())
return false;
- if (auto *VecTy = dyn_cast<VectorType>(DataTy)) {
+ if (auto *VecTy = dyn_cast<FixedVectorType>(DataTy)) {
// Don't support v2i1 yet.
if (VecTy->getNumElements() == 2)
return false;
@@ -854,7 +854,7 @@ int ARMTTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
return LT.first * BaseCost;
// Else this is expand, assume that we need to scalarize this op.
- if (auto *VTy = dyn_cast<VectorType>(Ty)) {
+ if (auto *VTy = dyn_cast<FixedVectorType>(Ty)) {
unsigned Num = VTy->getNumElements();
unsigned Cost = getArithmeticInstrCost(Opcode, Ty->getScalarType(),
CostKind);
@@ -898,8 +898,9 @@ int ARMTTIImpl::getInterleavedMemoryOpCost(
if (Factor <= TLI->getMaxSupportedInterleaveFactor() && !EltIs64Bits &&
!UseMaskForCond && !UseMaskForGaps) {
- unsigned NumElts = cast<VectorType>(VecTy)->getNumElements();
- auto *SubVecTy = VectorType::get(VecTy->getScalarType(), NumElts / Factor);
+ unsigned NumElts = cast<FixedVectorType>(VecTy)->getNumElements();
+ auto *SubVecTy =
+ FixedVectorType::get(VecTy->getScalarType(), NumElts / Factor);
// vldN/vstN only support legal vector types of size 64 or 128 in bits.
// Accesses having vector types that are a multiple of 128 bits can be
@@ -935,7 +936,7 @@ unsigned ARMTTIImpl::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
Alignment, CostKind, I);
assert(DataTy->isVectorTy() && "Can't do gather/scatters on scalar!");
- VectorType *VTy = cast<VectorType>(DataTy);
+ auto *VTy = cast<FixedVectorType>(DataTy);
// TODO: Splitting, once we do that.
@@ -1476,7 +1477,8 @@ bool ARMTTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
case Instruction::ICmp:
case Instruction::Add:
return ScalarBits < 64 &&
- (ScalarBits * cast<VectorType>(Ty)->getNumElements()) % 128 == 0;
+ (ScalarBits * cast<FixedVectorType>(Ty)->getNumElements()) % 128 ==
+ 0;
default:
llvm_unreachable("Unhandled reduction opcode");
}
diff --git a/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp b/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
index f5f9dc90bd55..5a0c4ca4cb3d 100644
--- a/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
+++ b/llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
@@ -188,8 +188,8 @@ Value *MVEGatherScatterLowering::checkGEP(Value *&Offsets, Type *Ty,
}
Offsets = GEP->getOperand(1);
// Paranoid check whether the number of parallel lanes is the same
- assert(cast<VectorType>(Ty)->getNumElements() ==
- cast<VectorType>(Offsets->getType())->getNumElements());
+ assert(cast<FixedVectorType>(Ty)->getNumElements() ==
+ cast<FixedVectorType>(Offsets->getType())->getNumElements());
// Only <N x i32> offsets can be integrated into an arm gather, any smaller
// type would have to be sign extended by the gep - and arm gathers can only
// zero extend. Additionally, the offsets do have to originate from a zext of
@@ -199,7 +199,7 @@ Value *MVEGatherScatterLowering::checkGEP(Value *&Offsets, Type *Ty,
return nullptr;
if (ZExtInst *ZextOffs = dyn_cast<ZExtInst>(Offsets))
Offsets = ZextOffs->getOperand(0);
- else if (!(cast<VectorType>(Offsets->getType())->getNumElements() == 4 &&
+ else if (!(cast<FixedVectorType>(Offsets->getType())->getNumElements() == 4 &&
Offsets->getType()->getScalarSizeInBits() == 32))
return nullptr;
@@ -222,8 +222,8 @@ Value *MVEGatherScatterLowering::checkGEP(Value *&Offsets, Type *Ty,
void MVEGatherScatterLowering::lookThroughBitcast(Value *&Ptr) {
// Look through bitcast instruction if #elements is the same
if (auto *BitCast = dyn_cast<BitCastInst>(Ptr)) {
- auto *BCTy = cast<VectorType>(BitCast->getType());
- auto *BCSrcTy = cast<VectorType>(BitCast->getOperand(0)->getType());
+ auto *BCTy = cast<FixedVectorType>(BitCast->getType());
+ auto *BCSrcTy = cast<FixedVectorType>(BitCast->getOperand(0)->getType());
if (BCTy->getNumElements() == BCSrcTy->getNumElements()) {
LLVM_DEBUG(
dbgs() << "masked gathers/scatters: looking through bitcast\n");
@@ -304,7 +304,7 @@ Value *MVEGatherScatterLowering::lowerGather(IntrinsicInst *I) {
// @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
// Attempt to turn the masked gather in I into a MVE intrinsic
// Potentially optimising the addressing modes as we do so.
- auto *Ty = cast<VectorType>(I->getType());
+ auto *Ty = cast<FixedVectorType>(I->getType());
Value *Ptr = I->getArgOperand(0);
unsigned Alignment = cast<ConstantInt>(I->getArgOperand(1))->getZExtValue();
Value *Mask = I->getArgOperand(2);
@@ -349,7 +349,7 @@ Value *MVEGatherScatterLowering::tryCreateMaskedGatherBase(IntrinsicInst *I,
IRBuilder<> &Builder,
int64_t Increment) {
using namespace PatternMatch;
- auto *Ty = cast<VectorType>(I->getType());
+ auto *Ty = cast<FixedVectorType>(I->getType());
LLVM_DEBUG(dbgs() << "masked gathers: loading from vector of pointers\n");
if (Ty->getNumElements() != 4 || Ty->getScalarSizeInBits() != 32)
// Can't build an intrinsic for this
@@ -369,7 +369,7 @@ Value *MVEGatherScatterLowering::tryCreateMaskedGatherBase(IntrinsicInst *I,
Value *MVEGatherScatterLowering::tryCreateMaskedGatherBaseWB(
IntrinsicInst *I, Value *Ptr, IRBuilder<> &Builder, int64_t Increment) {
using namespace PatternMatch;
- auto *Ty = cast<VectorType>(I->getType());
+ auto *Ty = cast<FixedVectorType>(I->getType());
LLVM_DEBUG(
dbgs()
<< "masked gathers: loading from vector of pointers with writeback\n");
@@ -467,7 +467,7 @@ Value *MVEGatherScatterLowering::lowerScatter(IntrinsicInst *I) {
Value *Input = I->getArgOperand(0);
Value *Ptr = I->getArgOperand(1);
unsigned Alignment = cast<ConstantInt>(I->getArgOperand(2))->getZExtValue();
- auto *Ty = cast<VectorType>(Input->getType());
+ auto *Ty = cast<FixedVectorType>(Input->getType());
if (!isLegalTypeAndAlignment(Ty->getNumElements(), Ty->getScalarSizeInBits(),
Alignment))
@@ -601,11 +601,11 @@ Value *MVEGatherScatterLowering::tryCreateMaskedScatterOffset(
Value *MVEGatherScatterLowering::tryCreateIncrementingGatScat(
IntrinsicInst *I, Value *BasePtr, Value *Offsets, GetElementPtrInst *GEP,
IRBuilder<> &Builder) {
- VectorType *Ty;
+ FixedVectorType *Ty;
if (I->getIntrinsicID() == Intrinsic::masked_gather)
- Ty = cast<VectorType>(I->getType());
+ Ty = cast<FixedVectorType>(I->getType());
else
- Ty = cast<VectorType>(I->getArgOperand(0)->getType());
+ Ty = cast<FixedVectorType>(I->getArgOperand(0)->getType());
// Incrementing gathers only exist for v4i32
if (Ty->getNumElements() != 4 ||
Ty->getScalarSizeInBits() != 32)
@@ -623,7 +623,7 @@ Value *MVEGatherScatterLowering::tryCreateIncrementingGatScat(
int TypeScale =
computeScale(DT.getTypeSizeInBits(GEP->getOperand(0)->getType()),
DT.getTypeSizeInBits(GEP->getType()) /
- cast<VectorType>(GEP->getType())->getNumElements());
+ cast<FixedVectorType>(GEP->getType())->getNumElements());
if (TypeScale == -1)
return nullptr;
@@ -702,7 +702,7 @@ Value *MVEGatherScatterLowering::tryCreateIncrementingWBGatScat(
Builder.SetInsertPoint(&Phi->getIncomingBlock(1 - IncrementIndex)->back());
unsigned NumElems =
- cast<VectorType>(OffsetsIncoming->getType())->getNumElements();
+ cast<FixedVectorType>(OffsetsIncoming->getType())->getNumElements();
// Make sure the offsets are scaled correctly
Instruction *ScaledOffsets = BinaryOperator::Create(
diff --git a/llvm/lib/Target/ARM/MVETailPredication.cpp b/llvm/lib/Target/ARM/MVETailPredication.cpp
index 9fbd8e58f454..ffc090e0cdc6 100644
--- a/llvm/lib/Target/ARM/MVETailPredication.cpp
+++ b/llvm/lib/Target/ARM/MVETailPredication.cpp
@@ -1,4 +1,4 @@
-//===- MVETailPredication.cpp - MVE Tail Predication ----------------------===//
+//===- MVETailPredication.cpp - MVE Tail Predication ------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -84,11 +84,11 @@ struct TripCountPattern {
Value *NumElements = nullptr;
// Other instructions in the icmp chain that calculate the predicate.
- VectorType *VecTy = nullptr;
+ FixedVectorType *VecTy = nullptr;
Instruction *Shuffle = nullptr;
Instruction *Induction = nullptr;
- TripCountPattern(Instruction *P, Value *TC, VectorType *VT)
+ TripCountPattern(Instruction *P, Value *TC, FixedVectorType *VT)
: Predicate(P), TripCount(TC), VecTy(VT){};
};
@@ -323,7 +323,7 @@ bool MVETailPredication::isTailPredicate(TripCountPattern &TCP) {
return false;
Value *InLoop = Phi->getIncomingValueForBlock(L->getLoopLatch());
- unsigned Lanes = cast<VectorType>(Insert->getType())->getNumElements();
+ unsigned Lanes = cast<FixedVectorType>(Insert->getType())->getNumElements();
Instruction *LHS = nullptr;
if (!match(InLoop, m_Add(m_Instruction(LHS), m_SpecificInt(Lanes))))
@@ -332,10 +332,10 @@ bool MVETailPredication::isTailPredicate(TripCountPattern &TCP) {
return LHS == Phi;
}
-static VectorType *getVectorType(IntrinsicInst *I) {
+static FixedVectorType *getVectorType(IntrinsicInst *I) {
unsigned TypeOp = I->getIntrinsicID() == Intrinsic::masked_load ? 0 : 1;
auto *PtrTy = cast<PointerType>(I->getOperand(TypeOp)->getType());
- return cast<VectorType>(PtrTy->getElementType());
+ return cast<FixedVectorType>(PtrTy->getElementType());
}
bool MVETailPredication::IsPredicatedVectorLoop() {
@@ -345,7 +345,7 @@ bool MVETailPredication::IsPredicatedVectorLoop() {
for (auto *BB : L->getBlocks()) {
for (auto &I : *BB) {
if (IsMasked(&I)) {
- VectorType *VecTy = getVectorType(cast<IntrinsicInst>(&I));
+ FixedVectorType *VecTy = getVectorType(cast<IntrinsicInst>(&I));
unsigned Lanes = VecTy->getNumElements();
unsigned ElementWidth = VecTy->getScalarSizeInBits();
// MVE vectors are 128-bit, but don't support 128 x i1.
More information about the llvm-commits
mailing list