[llvm] 5f3f45d - [Hexagon] Check isInstr() before getInstr() with SUnit

[Krzysztof Parzyszek via llvm-commits]

Author: Xinglong Liao
Date: 2020-05-14T08:47:54-05:00
New Revision: 5f3f45dc5338266f4e73bdbea2ce20fdb7142ded

URL: https://github.com/llvm/llvm-project/commit/5f3f45dc5338266f4e73bdbea2ce20fdb7142ded
DIFF: https://github.com/llvm/llvm-project/commit/5f3f45dc5338266f4e73bdbea2ce20fdb7142ded.diff

LOG: [Hexagon] Check isInstr() before getInstr() with SUnit

SUnit represent a MachineInstr in post-regalloc scheduling but SDNode
in pre-regalloc scheduling. when pass -enable-hexagon-sdnode-sched to
Hexagon backend with -O1 and above, this may cause an assertion failed.

Fixes PR45194.

Differential Revision: https://reviews.llvm.org/D76134

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 5f18767c76cc..2b7e1bcba9a3 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -318,11 +318,11 @@ bool HexagonSubtarget::useAA() const {
 void HexagonSubtarget::adjustSchedDependency(SUnit *Src, int SrcOpIdx,
                                              SUnit *Dst, int DstOpIdx,
                                              SDep &Dep) const {
-  MachineInstr *SrcInst = Src->getInstr();
-  MachineInstr *DstInst = Dst->getInstr();
   if (!Src->isInstr() || !Dst->isInstr())
     return;
 
+  MachineInstr *SrcInst = Src->getInstr();
+  MachineInstr *DstInst = Dst->getInstr();
   const HexagonInstrInfo *QII = getInstrInfo();
 
   // Instructions with .new operands have zero latency.