[PATCH] D79638: [llvm][SVE] IR intrinscs for matrix multiplication instructions.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:2273
+//
+def int_aarch64_sve_mmla : AdvSIMD_3VectorArg_Intrinsic;
+
----------------
Can you rename this intrinsic to `int_aarch64_sve_fmmla` to match the instruction and make it clear the intrinsic is only valid for FP values?


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:7603
+
+  def : Pat<(nxv4i32 (op (nxv4i32 ZPR32:$Zda), (nxv16i8 ZPR8:$Zn), (nxv16i8 ZPR8:$Zm))),
+            (!cast<Instruction>(NAME) ZPR32:$Zda, ZPR8:$Zn, ZPR8:$Zm)>;
----------------
Please use `SVE_3_Op_Pat` for these patterns.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:7678
+
+  def : Pat<(vt (op (vt zprty:$Zda), (vt zprty:$Zn), (vt zprty:$Zm))),
+            (!cast<Instruction>(NAME) zprty:$Zda, zprty:$Zn, zprty:$Zm)>;
----------------
Please use `SVE_3_Op_Pat` for these patterns.


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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-fp32.ll:3
+
+
+define <vscale x 4 x float> @fmmla_s(<vscale x 4 x float> %r, <vscale x 4 x float> %a, <vscale x 4 x float> %b) nounwind {
----------------
nit: unnecessary whitespace :)


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  https://reviews.llvm.org/D79638/new/

https://reviews.llvm.org/D79638