[llvm] 38e0ab2 - [X86] Don't allow f80 to be used with the 'q', 'r', 'l', 'Q' or 'q' inline assembly constraints.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-05-13T12:19:57-07:00
New Revision: 38e0ab2f3a3dc03acba37efe311c7c0a66665b79

URL: https://github.com/llvm/llvm-project/commit/38e0ab2f3a3dc03acba37efe311c7c0a66665b79
DIFF: https://github.com/llvm/llvm-project/commit/38e0ab2f3a3dc03acba37efe311c7c0a66665b79.diff

LOG: [X86] Don't allow f80 to be used with the 'q', 'r', 'l', 'Q' or 'q' inline assembly constraints.

It was previously trying to use the 64-bit class, but 80 isn't
evenly divisible by 64 so it will trigger a crash.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a6222353e055..34431fda1be6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48497,7 +48497,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
           return std::make_pair(0U, &X86::GR16RegClass);
         if (VT == MVT::i32 || VT == MVT::f32)
           return std::make_pair(0U, &X86::GR32RegClass);
-        return std::make_pair(0U, &X86::GR64RegClass);
+        if (VT != MVT::f80)
+          return std::make_pair(0U, &X86::GR64RegClass);
+        break;
       }
       LLVM_FALLTHROUGH;
       // 32-bit fallthrough
@@ -48508,7 +48510,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &X86::GR16_ABCDRegClass);
       if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
         return std::make_pair(0U, &X86::GR32_ABCDRegClass);
-      return std::make_pair(0U, &X86::GR64_ABCDRegClass);
+      if (VT != MVT::f80)
+        return std::make_pair(0U, &X86::GR64_ABCDRegClass);
+      break;
     case 'r':   // GENERAL_REGS
     case 'l':   // INDEX_REGS
       if (VT == MVT::i8 || VT == MVT::i1)
@@ -48517,7 +48521,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &X86::GR16RegClass);
       if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
         return std::make_pair(0U, &X86::GR32RegClass);
-      return std::make_pair(0U, &X86::GR64RegClass);
+      if (VT != MVT::f80)
+        return std::make_pair(0U, &X86::GR64RegClass);
+      break;
     case 'R':   // LEGACY_REGS
       if (VT == MVT::i8 || VT == MVT::i1)
         return std::make_pair(0U, &X86::GR8_NOREXRegClass);
@@ -48525,7 +48531,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         return std::make_pair(0U, &X86::GR16_NOREXRegClass);
       if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget.is64Bit())
         return std::make_pair(0U, &X86::GR32_NOREXRegClass);
-      return std::make_pair(0U, &X86::GR64_NOREXRegClass);
+      if (VT != MVT::f80)
+        return std::make_pair(0U, &X86::GR64_NOREXRegClass);
+      break;
     case 'f':  // FP Stack registers.
       // If SSE is enabled for this VT, use f80 to ensure the isel moves the
       // value to the correct fpstack register class.

diff  --git a/llvm/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll b/llvm/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
index c7e86f565eef..a6f9f9a29ea8 100644
--- a/llvm/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
+++ b/llvm/test/CodeGen/X86/asm-reject-reg-type-mismatch.ll
@@ -6,3 +6,9 @@ define i128 @blup() {
   %v = tail call i128 asm "", "={ax},0"(i128 0)
   ret i128 %v
 }
+
+; CHECK: error: couldn't allocate input reg for constraint 'r'
+define void @fp80(x86_fp80) {
+  tail call void asm sideeffect "", "r"(x86_fp80 %0)
+  ret void
+}