[llvm] 18a5428 - [AMDGPU][MC][GFX9+] Enabled clamp for v_add_i32 and v_sub_i32
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Wed May 13 04:18:00 PDT 2020
Author: Dmitry Preobrazhensky
Date: 2020-05-13T14:17:20+03:00
New Revision: 18a5428e60272482e7a3855fbfd40427e8066be6
URL: https://github.com/llvm/llvm-project/commit/18a5428e60272482e7a3855fbfd40427e8066be6
DIFF: https://github.com/llvm/llvm-project/commit/18a5428e60272482e7a3855fbfd40427e8066be6.diff
LOG: [AMDGPU][MC][GFX9+] Enabled clamp for v_add_i32 and v_sub_i32
See bug 45830: https://bugs.llvm.org/show_bug.cgi?id=45830
Reviewers: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D79585
Added:
Modified:
llvm/lib/Target/AMDGPU/VOP3Instructions.td
llvm/test/MC/AMDGPU/gfx10_asm_all.s
llvm/test/MC/AMDGPU/vop3-gfx9.s
llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 3428c6416366..249eb69ba4c9 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -630,8 +630,8 @@ def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32,
def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
-def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
-def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
+def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
+def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32_ARITH>>;
class ThreeOp_i32_Pats <SDPatternOperator op1, SDPatternOperator op2, Instruction inst> : GCNPat <
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_all.s b/llvm/test/MC/AMDGPU/gfx10_asm_all.s
index 8b61ad8c91a3..d99bdacdfc01 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_all.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_all.s
@@ -62887,6 +62887,9 @@ v_sub_nc_i32 v5, v1, 0.5
v_sub_nc_i32 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x01,0x00]
+v_sub_nc_i32 v5, v1, -4.0 clamp
+// GFX10: v_sub_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x76,0xd7,0x01,0xef,0x01,0x00]
+
v_permlane16_b32 v5, v1, v2, v3
// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
@@ -63223,6 +63226,9 @@ v_add_nc_i32 v5, v1, 0.5
v_add_nc_i32 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x01,0x00]
+v_add_nc_i32 v5, v1, -4.0 clamp
+// GFX10: v_add_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x7f,0xd7,0x01,0xef,0x01,0x00]
+
v_pk_fmac_f16 v5, v1, v2
// GFX10: encoding: [0x01,0x05,0x0a,0x78]
diff --git a/llvm/test/MC/AMDGPU/vop3-gfx9.s b/llvm/test/MC/AMDGPU/vop3-gfx9.s
index bec430e88192..26148b8c50f2 100644
--- a/llvm/test/MC/AMDGPU/vop3-gfx9.s
+++ b/llvm/test/MC/AMDGPU/vop3-gfx9.s
@@ -515,6 +515,22 @@ v_subrev_co_u32 v84, vcc, v13, v31
// GFX9: v_subrev_co_u32_e32 v84, vcc, v13, v31 ; encoding: [0x0d,0x3f,0xa8,0x36]
// NOVI: error: instruction not supported on this GPU
+v_add_i32 v1, v2, v3
+// GFX9: v_add_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x9c,0xd2,0x02,0x07,0x02,0x00]
+// NOVI: error: instruction not supported on this GPU
+
+v_add_i32 v1, v2, v3 clamp
+// GFX9: v_add_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00]
+// NOVI: error: invalid operand for instruction
+
+v_sub_i32 v1, v2, v3
+// GFX9: v_sub_i32 v1, v2, v3 ; encoding: [0x01,0x00,0x9d,0xd2,0x02,0x07,0x02,0x00]
+// NOVI: error: instruction not supported on this GPU
+
+v_sub_i32 v1, v2, v3 clamp
+// GFX9: v_sub_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00]
+// NOVI: error: invalid operand for instruction
+
//===----------------------------------------------------------------------===//
// Validate register size checks (bug 37943)
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
index 3e0404609884..5a8153aaf05c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt
@@ -21320,6 +21320,9 @@
# GFX10: v_add_nc_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00
+# GFX10: v_add_nc_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x7f,0xd7,0x02,0x07,0x02,0x00]
+0x01,0x80,0x7f,0xd7,0x02,0x07,0x02,0x00
+
# GFX10: v_add_nc_u16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00
@@ -95718,6 +95721,9 @@
# GFX10: v_sub_nc_i32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00]
0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00
+# GFX10: v_sub_nc_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x76,0xd7,0x02,0x07,0x02,0x00]
+0x01,0x80,0x76,0xd7,0x02,0x07,0x02,0x00
+
# GFX10: v_sub_nc_u16_e64 v255, v1, v2 ; encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt b/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
index fc028a2a60c2..98edee4881f3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
@@ -723,3 +723,8 @@
# GFX9: v_subrev_co_u32_e64 v84, vcc, v13, v31 clamp ; encoding: [0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00]
0x54,0xea,0x1b,0xd1,0x0d,0x3f,0x02,0x00
+# GFX9: v_add_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00]
+0x01,0x80,0x9c,0xd2,0x02,0x07,0x02,0x00
+
+# GFX9: v_sub_i32 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00]
+0x01,0x80,0x9d,0xd2,0x02,0x07,0x02,0x00
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