[PATCH] D78471: [x86/SLH] Pin function address in physical register after it been hardened.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei updated this revision to Diff 263640.
pengfei added a comment.

Copy the symbol only. Thanks @craig.topper 's suggestion and @chandlerc 's interpretation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78471/new/

https://reviews.llvm.org/D78471

Files:
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll


Index: llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
===================================================================
--- llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
+++ llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
@@ -2,8 +2,8 @@
 
 define i32 @foo(void ()** %0) {
 ; CHECK-LABEL: foo:
-; CHECK-NOT:    .Lslh_ret_addr0:
 ; CHECK:         callq *(%{{.*}})
+; CHECK-NEXT:  .Lslh_ret_addr0:
 ; CHECK-NEXT:    movq %rsp, %rcx
 ; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    sarq $63, %rcx
Index: llvm/lib/CodeGen/TargetInstrInfo.cpp
===================================================================
--- llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -596,6 +596,7 @@
         MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI),
                                 Flags, MemSize, MFI.getObjectAlign(FI));
     NewMI->addMemOperand(MF, MMO);
+    NewMI->cloneInstrSymbols(MF, MI);
 
     return NewMI;
   }


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