[PATCH] D79761: [AMDGPU] Add AGPRs to getRegClassForSizeOnBank

[Austin Kerbow via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9f0b736126cb: [AMDGPU] Add AGPRs to getRegClassForSizeOnBank (authored by kerbowa).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79761/new/

https://reviews.llvm.org/D79761

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp


Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1720,6 +1720,8 @@
                     : &AMDGPU::SReg_64_XEXECRegClass;
   case AMDGPU::SGPRRegBankID:
     return getSGPRClassForBitWidth(std::max(32u, Size));
+  case AMDGPU::AGPRRegBankID:
+    return getAGPRClassForBitWidth(std::max(32u, Size));
   default:
     llvm_unreachable("unknown register bank");
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D79761.263471.patch
Type: text/x-patch
Size: 529 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200512/62d26a0e/attachment.bin>