[PATCH] D79794: Change the INLINEASM_BR MachineInstr to be a non-terminating instruction.

[James Y Knight via Phabricator via llvm-commits]

jyknight created this revision.
jyknight added reviewers: nickdesaulniers, void, arsenm, qcolombet, efriedma.
Herald added subscribers: llvm-commits, tpr, kbarton, hiraditya, wdng, nemanjai, MatzeB.
Herald added a project: LLVM.
jyknight added a parent revision: D79793: Simplify MachineVerifier's block-successor verification..
Herald added a subscriber: wuzish.
jyknight added a parent revision: D79605: MachineBasicBlock::updateTerminator now requires an explicit layout successor..

Before this instruction supported output values, it fit fairly
naturally as a terminator. However, being a terminator while also
supporting outputs causes some trouble, as the physreg->vreg COPY
operations cannot be in the same block.

Modeling it as a non-terminator allows it to be handled the same way
as invoke is handled already.

Most of the changes here were created by auditing all the existing
users of MachineBasicBlock::isEHPad() and
MachineBasicBlock::hasEHPadSuccessor(), and adding calls to
isInlineAsmBrIndirectTarget or hasInlineAsmBr, as appropriate.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79794

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/include/llvm/CodeGen/MachineBasicBlock.h
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/BranchFolding.cpp
  llvm/lib/CodeGen/MachineBasicBlock.cpp
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/lib/CodeGen/PHIEliminationUtils.cpp
  llvm/lib/CodeGen/RegisterCoalescer.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
  llvm/lib/CodeGen/ShrinkWrap.cpp
  llvm/lib/CodeGen/SplitKit.cpp
  llvm/lib/CodeGen/SplitKit.h
  llvm/lib/CodeGen/TailDuplicator.cpp
  llvm/lib/Target/Hexagon/BitTracker.cpp
  llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/test/CodeGen/AArch64/callbr-asm-label.ll
  llvm/test/CodeGen/AArch64/callbr-asm-obj-file.ll
  llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
  llvm/test/CodeGen/ARM/ifcvt-size.mir
  llvm/test/CodeGen/X86/callbr-asm-blockplacement.ll
  llvm/test/CodeGen/X86/callbr-asm-branch-folding.ll
  llvm/test/CodeGen/X86/callbr-asm-label-addr.ll
  llvm/test/CodeGen/X86/callbr-asm-outputs-pred-succ.ll
  llvm/test/CodeGen/X86/callbr-asm-outputs.ll
  llvm/test/CodeGen/X86/callbr-asm.ll
  llvm/test/CodeGen/X86/shrinkwrap-callbr.ll
  llvm/test/Verifier/callbr.ll

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