[llvm] f242950 - Fold single-use variables into assert

[Benjamin Kramer via llvm-commits]

Author: Benjamin Kramer
Date: 2020-05-12T15:26:59+02:00
New Revision: f242950fdf7ca5b84d3cadc9a57588af3621e1e8

URL: https://github.com/llvm/llvm-project/commit/f242950fdf7ca5b84d3cadc9a57588af3621e1e8
DIFF: https://github.com/llvm/llvm-project/commit/f242950fdf7ca5b84d3cadc9a57588af3621e1e8.diff

LOG: Fold single-use variables into assert

This avoids unused variable warnings in Release builds.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 899b18f90aee..fbd9ba27a9d2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3180,9 +3180,7 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     if (!Ty.isVector())
       report_fatal_error("Unexpected type for aarch64_neon_vsli");
 
-    uint64_t ShiftAmount = Op.getConstantOperandVal(3);
-    unsigned ElemSizeInBits = Ty.getScalarSizeInBits();
-    assert(ShiftAmount <= ElemSizeInBits);
+    assert(Op.getConstantOperandVal(3) <= Ty.getScalarSizeInBits());
 
     bool IsShiftRight = IntNo == Intrinsic::aarch64_neon_vsri;
     unsigned Opcode = IsShiftRight ? AArch64ISD::VSRI : AArch64ISD::VSLI;

diff  --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 0266b50dfed7..17b2c3584751 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -749,9 +749,8 @@ void llvm::recomputeVPTBlockMask(MachineInstr &Instr) {
 
   // Verify that the instruction after the VPT/VPST is predicated (it should
   // be), and skip it.
-  ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*Iter);
   assert(
-      Pred == ARMVCC::Then &&
+      getVPTInstrPredicate(*Iter) == ARMVCC::Then &&
       "VPT/VPST should be followed by an instruction with a 'then' predicate!");
   ++Iter;