[llvm] 0387df7 - [X86] combineX86ShuffleChain - use narrowShuffleMaskElts scale == 1 builtin handling. NFC.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Tue May 12 05:47:00 PDT 2020


Author: Simon Pilgrim
Date: 2020-05-12T13:45:40+01:00
New Revision: 0387df7f02f9a0a0239b5a90f840e98b823bc6c1

URL: https://github.com/llvm/llvm-project/commit/0387df7f02f9a0a0239b5a90f840e98b823bc6c1
DIFF: https://github.com/llvm/llvm-project/commit/0387df7f02f9a0a0239b5a90f840e98b823bc6c1.diff

LOG: [X86] combineX86ShuffleChain - use narrowShuffleMaskElts scale == 1 builtin handling. NFC.

narrowShuffleMaskElts already has the fast-path for scale == 1, no need to reimplement it here.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 42723a0dc8ee..7b8a62c9c0af 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34128,14 +34128,10 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
       return DAG.getBitcast(RootVT, Res);
     }
 
+    // Narrow shuffle mask to v4x128.
     SmallVector<int, 4> Mask;
-    if (BaseMaskEltSizeInBits > 128) {
-      assert((BaseMaskEltSizeInBits % 128) == 0 && "Illegal mask size");
-      int MaskScale = BaseMaskEltSizeInBits / 128;
-      narrowShuffleMaskElts(MaskScale, BaseMask, Mask);
-    } else {
-      Mask.assign(BaseMask.begin(), BaseMask.end());
-    }
+    assert((BaseMaskEltSizeInBits % 128) == 0 && "Illegal mask size");
+    narrowShuffleMaskElts(BaseMaskEltSizeInBits / 128, BaseMask, Mask);
 
     // Try to lower to vshuf64x2/vshuf32x4.
     auto MatchSHUF128 = [](MVT ShuffleVT, const SDLoc &DL, ArrayRef<int> Mask,


        


More information about the llvm-commits mailing list