[llvm] 9d6064e - Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance"

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2020-05-12T18:49:17+08:00
New Revision: 9d6064ec49ec189d2ff032927e41bb90ac471ae1

URL: https://github.com/llvm/llvm-project/commit/9d6064ec49ec189d2ff032927e41bb90ac471ae1
DIFF: https://github.com/llvm/llvm-project/commit/9d6064ec49ec189d2ff032927e41bb90ac471ae1.diff

LOG: Revert "[RISCV] Make CanLowerReturn protected for downstream maintenance"

This reverts commit d775841d7d6ee3e8bbf3a420590be9bb19433eaa.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 825f39767942..0927a3e2ed0f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -161,13 +161,6 @@ class RISCVTargetLowering : public TargetLowering {
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
 
-protected:
-  // This method is protected for customizing and reusing by inherited class.
-  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
-                      bool IsVarArg,
-                      const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
-
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -181,6 +174,10 @@ class RISCVTargetLowering : public TargetLowering {
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                const SDLoc &DL, SelectionDAG &DAG,
                                SmallVectorImpl<SDValue> &InVals) const override;
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool IsVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,