[PATCH] D78545: [RISCV] Make CanLowerReturn protected for downstream maintenance
Jim Lin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 11 23:12:22 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd775841d7d6e: [RISCV] Make CanLowerReturn protected for downstream maintenance (authored by Jim).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78545/new/
https://reviews.llvm.org/D78545
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.h
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -161,6 +161,13 @@
Register getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const override;
+protected:
+ // This method is protected for customizing and reusing by inherited class.
+ bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+ bool IsVarArg,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext &Context) const override;
+
private:
void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -174,10 +181,6 @@
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &DL, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const override;
- bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
- bool IsVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs,
- LLVMContext &Context) const override;
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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