[llvm] d775841 - [RISCV] Make CanLowerReturn protected for downstream maintenance

[Jim Lin via llvm-commits]

Author: Jim Lin
Date: 2020-05-12T13:50:42+08:00
New Revision: d775841d7d6ee3e8bbf3a420590be9bb19433eaa

URL: https://github.com/llvm/llvm-project/commit/d775841d7d6ee3e8bbf3a420590be9bb19433eaa
DIFF: https://github.com/llvm/llvm-project/commit/d775841d7d6ee3e8bbf3a420590be9bb19433eaa.diff

LOG: [RISCV] Make CanLowerReturn protected for downstream maintenance

Summary: For the downstream RISCV maintenance, it would be easier to override and reuse CanLowerReturn for customizing.

Reviewers: asb, lenary, luismarques

Reviewed By: lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, s.egerton, pzheng, sameer.abuasal, apazos, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78545

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 0927a3e2ed0f..825f39767942 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -161,6 +161,13 @@ class RISCVTargetLowering : public TargetLowering {
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
 
+protected:
+  // This method is protected for customizing and reusing by inherited class.
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool IsVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
@@ -174,10 +181,6 @@ class RISCVTargetLowering : public TargetLowering {
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                const SDLoc &DL, SelectionDAG &DAG,
                                SmallVectorImpl<SDValue> &InVals) const override;
-  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
-                      bool IsVarArg,
-                      const SmallVectorImpl<ISD::OutputArg> &Outs,
-                      LLVMContext &Context) const override;
   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,