[PATCH] D78471: [x86/SLH] Pin function address in physical register after it been hardened.

[Pengfei Wang via Phabricator via llvm-commits]

pengfei updated this revision to Diff 263345.
pengfei added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78471/new/

https://reviews.llvm.org/D78471

Files:
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll


Index: llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
===================================================================
--- llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
+++ llvm/test/CodeGen/X86/speculative-load-hardening-no-spill.ll
@@ -2,8 +2,8 @@
 
 define i32 @foo(void ()** %0) {
 ; CHECK-LABEL: foo:
-; CHECK-NOT:    .Lslh_ret_addr0:
-; CHECK:         callq *(%{{.*}})
+; CHECK:         callq *%{{.*}}
+; CHECK-NEXT:  .Lslh_ret_addr0:
 ; CHECK-NEXT:    movq %rsp, %rcx
 ; CHECK-NEXT:    movq -{{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    sarq $63, %rcx
Index: llvm/lib/CodeGen/LiveIntervals.cpp
===================================================================
--- llvm/lib/CodeGen/LiveIntervals.cpp
+++ llvm/lib/CodeGen/LiveIntervals.cpp
@@ -862,6 +862,11 @@
 float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
                                     const MachineBlockFrequencyInfo *MBFI,
                                     const MachineInstr &MI) {
+  // FIXME: Is there place to add the check better than here?
+  // The pass x86-slh attached an post instruction symbol to call instruction.
+  // We don't want its register been spilt out.
+  if (MI.isCall() && MI.getPostInstrSymbol())
+    return huge_valf;
   return getSpillWeight(isDef, isUse, MBFI, MI.getParent());
 }
 


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