[PATCH] D79716: [CodeGen] Fix bug in inline asm reserved register detection

[Victor Campos via Phabricator via llvm-commits]

vhscampos created this revision.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls.
Herald added a project: LLVM.

In the case where inline asm's input operands are assigned values,
targets may opt to emit an error when a reserved register is used for
such operands. This is the case for Arm.

The current code, however, emits an error even when the reserved
register, when used as an input operand, is only read from. This is a
bug.

This patch adds additional checks to emit error only when a reserved
register used as an input operand is actually written to. The criteria
used is to check whether or not the input operand value, which is the
value to be loaded into the input, is undef. When this is the case, the
assignment is optimized away and therefore the reserved register ends up
not being written to.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79716

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/ARM/inline-asm-reserved-registers.ll


Index: llvm/test/CodeGen/ARM/inline-asm-reserved-registers.ll
===================================================================
--- llvm/test/CodeGen/ARM/inline-asm-reserved-registers.ll
+++ llvm/test/CodeGen/ARM/inline-asm-reserved-registers.ll
@@ -43,3 +43,10 @@
   %0 = call i32 asm sideeffect "mov $0, $1", "=r,{r6}"(i32 %input)
   ret void
 }
+
+; CHECK-ERROR-NOT: error: write to reserved register 'PC'
+define void @test_input_read() {
+entry:
+  %0 = call i32 asm sideeffect "mov $0, $1", "=r,{pc}"(i32 undef)
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8150,7 +8150,7 @@
             : OpInfo;
     GetRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
 
-    auto DetectWriteToReservedRegister = [&]() {
+    auto DetectReservedRegister = [&]() {
       const MachineFunction &MF = DAG.getMachineFunction();
       const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
       for (unsigned Reg : OpInfo.AssignedRegs.Regs) {
@@ -8190,7 +8190,7 @@
           return;
         }
 
-        if (DetectWriteToReservedRegister())
+        if (DetectReservedRegister())
           return;
 
         // Add information to the INLINEASM node to know that this register is
@@ -8339,7 +8339,9 @@
         return;
       }
 
-      if (DetectWriteToReservedRegister())
+      // Detect the case where the input operand value would lead to a reserved
+      // register being written to.
+      if (InOperandVal && !InOperandVal.isUndef() && DetectReservedRegister())
         return;
 
       SDLoc dl = getCurSDLoc();


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