[llvm] f40fc7b - [X86] Fix combineVectorCompareAndMaskUnaryOp regression after 0e8e731449d8fbfa6ba4523de928b4812ef9f100

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2020-05-10T19:03:38-07:00
New Revision: f40fc7b8d60e6897fd9514a46a26f4b84f57577a

URL: https://github.com/llvm/llvm-project/commit/f40fc7b8d60e6897fd9514a46a26f4b84f57577a
DIFF: https://github.com/llvm/llvm-project/commit/f40fc7b8d60e6897fd9514a46a26f4b84f57577a.diff

LOG: [X86] Fix combineVectorCompareAndMaskUnaryOp regression after 0e8e731449d8fbfa6ba4523de928b4812ef9f100

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 564e6de262b7..09a4f70da4fa 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45586,7 +45586,8 @@ static SDValue combineVectorCompareAndMaskUnaryOp(SDNode *N,
   unsigned NumEltBits = VT.getScalarSizeInBits();
   SDValue Op0 = N->getOperand(IsStrict ? 1 : 0);
   if (!VT.isVector() || Op0.getOpcode() != ISD::AND ||
-      DAG.ComputeNumSignBits(Op0.getOperand(0)) != NumEltBits)
+      DAG.ComputeNumSignBits(Op0.getOperand(0)) != NumEltBits ||
+      VT.getSizeInBits() != Op0.getValueSizeInBits())
     return SDValue();
 
   // Now check that the other operand of the AND is a constant. We could

diff  --git a/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll b/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
index 365ae9a61c27..6f335c00b589 100644
--- a/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
+++ b/llvm/test/CodeGen/X86/x86-setcc-int-to-fp-combine.ll
@@ -138,3 +138,33 @@ define <4 x float> @foo6(<4 x i32> %a0, <4 x i32> %a1) {
   %6 = uitofp <4 x i32> %5 to <4 x float>
   ret <4 x float> %6
 }
+
+define <4 x float> @foo7(<4 x i64> %a) {
+; CHECK-LABEL: LCPI7_0:
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   255                     ## 0xff
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   255                     ## 0xff
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   255                     ## 0xff
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   255                     ## 0xff
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-NEXT:  .byte   0                       ## 0x0
+; CHECK-LABEL: foo7:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
+; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    cvtdq2ps %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %b = and <4 x i64> %a, <i64 4278255360, i64 4278255360, i64 4278255360, i64 4278255360>
+  %c = and <4 x i64> %b, <i64 65535, i64 65535, i64 65535, i64 65535>
+  %d = uitofp <4 x i64> %c to <4 x float>
+  ret <4 x float> %d
+}