[llvm] f66309d - [GlobalISel] Don't add duplicate successors to MBBs when translating indirectbr

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2020-05-08T13:40:02-07:00
New Revision: f66309deab1d99a17d6740244dfd1b9f959e9095

URL: https://github.com/llvm/llvm-project/commit/f66309deab1d99a17d6740244dfd1b9f959e9095
DIFF: https://github.com/llvm/llvm-project/commit/f66309deab1d99a17d6740244dfd1b9f959e9095.diff

LOG: [GlobalISel] Don't add duplicate successors to MBBs when translating indirectbr

This fixes a verifier failure on a bot:

http://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-aarch64-O0-g/

```
*** Bad machine code: MBB has duplicate entries in its successor list. ***
- function:    foo
- basic block: %bb.5 indirectgoto (0x7fe3d687ca08)
```

One of the GCC torture suite tests (pr70460.c) has an indirectbr instruction
which has duplicate blocks in its destination list.

According to the langref this is allowed:

> Blocks are allowed to occur multiple times in the destination list, though
> this isn’t particularly useful.
(https://www.llvm.org/docs/LangRef.html#indirectbr-instruction)

We don't allow this in MIR. So, when we translate such an instruction, the
verifier screams.

This patch makes `translateIndirectBr` check if a successor has already been
added to a block. If the successor is present, it is skipped rather than added
twice.

Differential Revision: https://reviews.llvm.org/D79609

Added: 
    llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll

Modified: 
    llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index ca4f353d83e7..230f6d6965e9 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -838,9 +838,16 @@ bool IRTranslator::translateIndirectBr(const User &U,
   MIRBuilder.buildBrIndirect(Tgt);
 
   // Link successors.
+  SmallPtrSet<const BasicBlock *, 32> AddedSuccessors;
   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
-  for (const BasicBlock *Succ : successors(&BrInst))
+  for (const BasicBlock *Succ : successors(&BrInst)) {
+    // It's legal for indirectbr instructions to have duplicate blocks in the
+    // destination list. We don't allow this in MIR. Skip anything that's
+    // already a successor.
+    if (!AddedSuccessors.insert(Succ).second)
+      continue;
     CurBB.addSuccessor(&getMBB(*Succ));
+  }
 
   return true;
 }

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll
new file mode 100644
index 000000000000..bef15631a231
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-indirect-br-repeated-block.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=aarch64-apple-ios -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
+;
+; Make sure that we don't duplicate successors/predecessors when translating
+; indirectbr instructions with duplicate block labels.
+
+define void @foo() {
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   successors: %bb.2(0x2aaaaaaa), %bb.4(0x2aaaaaaa), %bb.3(0x2aaaaaaa)
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+  ; CHECK:   G_BRINDIRECT [[DEF]](p0)
+  ; CHECK: bb.2 (%ir-block.1):
+  ; CHECK:   successors:
+  ; CHECK: bb.3 (%ir-block.2):
+  ; CHECK:   successors:
+  ; CHECK: bb.4 (%ir-block.3):
+  ; CHECK:   RET_ReallyLR
+  indirectbr i8* undef, [label %1, label %3, label %2, label %3, label %3]
+1:
+  unreachable
+2:
+  unreachable
+3:
+  ret void
+}