[llvm] 5fa87ec - [AMDGPU] Try to determine sign bit during div/rem expansion

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2020-05-08T10:11:26+02:00
New Revision: 5fa87ec004fd8a493ee6799ee5ba81b1c82daf19

URL: https://github.com/llvm/llvm-project/commit/5fa87ec004fd8a493ee6799ee5ba81b1c82daf19
DIFF: https://github.com/llvm/llvm-project/commit/5fa87ec004fd8a493ee6799ee5ba81b1c82daf19.diff

LOG: [AMDGPU] Try to determine sign bit during div/rem expansion

This is preparation for D79294, which removes an expensive
InstSimplify optimization, on the assumption that it will be
picked up by InstCombine instead. Of course, this does not hold
up if a backend performs non-trivial IR expansions without running
a canonicalization pipeline afterwards, which turned up as an
issue in the context of AMDGPU div/rem expansion.

This patch mitigates the issue by explicitly performing a known
bits calculation where it matters. No test changes, as those would
only be visible after the other patch lands.

Differential Revision: https://reviews.llvm.org/D79596

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index fef649f6b3fd..1acc7b02fbcf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -1005,6 +1005,16 @@ bool AMDGPUCodeGenPrepare::divHasSpecialOptimization(
   return false;
 }
 
+static Value *getSign32(Value *V, IRBuilder<> &Builder, const DataLayout *DL) {
+  // Check whether the sign can be determined statically.
+  KnownBits Known = computeKnownBits(V, *DL);
+  if (Known.isNegative())
+    return Constant::getAllOnesValue(V->getType());
+  if (Known.isNonNegative())
+    return Constant::getNullValue(V->getType());
+  return Builder.CreateAShr(V, Builder.getInt32(31));
+}
+
 Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
                                             BinaryOperator &I,
                                             Value *Num, Value *Den) const {
@@ -1046,9 +1056,8 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
 
   Value *Sign = nullptr;
   if (IsSigned) {
-    ConstantInt *K31 = Builder.getInt32(31);
-    Value *LHSign = Builder.CreateAShr(Num, K31);
-    Value *RHSign = Builder.CreateAShr(Den, K31);
+    Value *LHSign = getSign32(Num, Builder, DL);
+    Value *RHSign = getSign32(Den, Builder, DL);
     // Remainder sign is the same as LHS
     Sign = IsDiv ? Builder.CreateXor(LHSign, RHSign) : LHSign;