[llvm] 5b48f7d - [VectorCombine] adjust test to make intent clearer; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-05-07T16:21:17-04:00
New Revision: 5b48f7d2fc185ecd262aae43ddcfa32294205ca6

URL: https://github.com/llvm/llvm-project/commit/5b48f7d2fc185ecd262aae43ddcfa32294205ca6
DIFF: https://github.com/llvm/llvm-project/commit/5b48f7d2fc185ecd262aae43ddcfa32294205ca6.diff

LOG: [VectorCombine] adjust test to make intent clearer; NFC

Create a non-zero result to show that the other lane is computed correctly.

Added: 
    

Modified: 
    llvm/test/Transforms/VectorCombine/X86/insert-binop.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/VectorCombine/X86/insert-binop.ll b/llvm/test/Transforms/VectorCombine/X86/insert-binop.ll
index 1ab1457536ff..8136de8b3037 100644
--- a/llvm/test/Transforms/VectorCombine/X86/insert-binop.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/insert-binop.ll
@@ -101,16 +101,16 @@ define <2 x i64> @ins1_ins1_sdiv(i64 %x, i64 %y) {
   ret <2 x i64> %r
 }
 
-define <2 x i64> @ins1_ins1_srem(i64 %x, i64 %y) {
-; CHECK-LABEL: @ins1_ins1_srem(
-; CHECK-NEXT:    [[I0:%.*]] = insertelement <2 x i64> <i64 42, i64 undef>, i64 [[X:%.*]], i64 1
-; CHECK-NEXT:    [[I1:%.*]] = insertelement <2 x i64> <i64 -7, i64 undef>, i64 [[Y:%.*]], i32 1
-; CHECK-NEXT:    [[R:%.*]] = srem <2 x i64> [[I0]], [[I1]]
+define <2 x i64> @ins1_ins1_udiv(i64 %x, i64 %y) {
+; CHECK-LABEL: @ins1_ins1_udiv(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <2 x i64> <i64 42, i64 undef>, i64 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <2 x i64> <i64 7, i64 undef>, i64 [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[R:%.*]] = udiv <2 x i64> [[I0]], [[I1]]
 ; CHECK-NEXT:    ret <2 x i64> [[R]]
 ;
-  %i0 = insertelement <2 x i64> <i64 42, i64 undef>, i64 %x, i64 1
-  %i1 = insertelement <2 x i64> <i64 -7, i64 undef>, i64 %y, i32 1
-  %r = srem <2 x i64> %i0, %i1
+  %i0 = insertelement <2 x i64> <i64 42, i64 undef>, i64 %x, i32 1
+  %i1 = insertelement <2 x i64> <i64 7, i64 undef>, i64 %y, i32 1
+  %r = udiv <2 x i64> %i0, %i1
   ret <2 x i64> %r
 }