[llvm] 62ea77e - [SLP] add test for constant expression fake of load-combine pattern; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-05-07T15:04:37-04:00
New Revision: 62ea77ec022b8d598a0e213db2e22a2b79063f80

URL: https://github.com/llvm/llvm-project/commit/62ea77ec022b8d598a0e213db2e22a2b79063f80
DIFF: https://github.com/llvm/llvm-project/commit/62ea77ec022b8d598a0e213db2e22a2b79063f80.diff

LOG: [SLP] add test for constant expression fake of load-combine pattern; NFC

This is a reduction of the test that caused D78997 to be reverted.

Added: 
    

Modified: 
    llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll b/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
index fb206b84fa93..e0b626e879c9 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bad-reduction.ll
@@ -503,3 +503,21 @@ define void @PR39538(i8* %t0, i32* %t1) {
   store i32 %t75, i32* %t76, align 4
   ret void
 }
+
+; Do not crash on constant expressions.
+
+ at g1 = external dso_local unnamed_addr constant [8 x i8], align 1
+ at g2 = external dso_local unnamed_addr constant [5 x i8], align 1
+
+define void @load_combine_constant_expression(i64* %t1) {
+; CHECK-LABEL: @load_combine_constant_expression(
+; CHECK-NEXT:    store i64 or (i64 shl (i64 zext (i32 ptrtoint ([8 x i8]* @g1 to i32) to i64), i64 32), i64 zext (i32 ptrtoint ([5 x i8]* @g2 to i32) to i64)), i64* [[T1:%.*]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = getelementptr i64, i64* [[T1]], i64 1
+; CHECK-NEXT:    store i64 or (i64 shl (i64 zext (i32 ptrtoint ([8 x i8]* @g1 to i32) to i64), i64 32), i64 zext (i32 ptrtoint ([5 x i8]* @g2 to i32) to i64)), i64* [[T3]], align 4
+; CHECK-NEXT:    ret void
+;
+  store i64 or (i64 shl (i64 zext (i32 ptrtoint ([8 x i8]* @g1 to i32) to i64), i64 32), i64 zext (i32 ptrtoint ([5 x i8]* @g2 to i32) to i64)), i64* %t1, align 4
+  %t3 = getelementptr i64, i64* %t1, i64 1
+  store i64 or (i64 shl (i64 zext (i32 ptrtoint ([8 x i8]* @g1 to i32) to i64), i64 32), i64 zext (i32 ptrtoint ([5 x i8]* @g2 to i32) to i64)), i64* %t3, align 4
+  ret void
+}