[PATCH] D74794: [X86][ISelLowering] refactor Varargs handling in X86ISelLowering.cpp

[Arthur Eubanks via Phabricator via llvm-commits]

aeubanks added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:3380-3393
+struct VarArgRegsDescr {
+  ArrayRef<MCPhysReg> ArgGPRs; // all GPR registers used for passing varargs
+  ArrayRef<MCPhysReg> ArgXMMs; // all XMM registers used for passing varargs
+  unsigned NumIntRegs = 0;     // number of allocated GPRs
+  unsigned NumXMMRegs = 0;     // number of allocated XMMs
+
+  ArrayRef<MCPhysReg> getAvailableIntRegs() {
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avl wrote:
> aeubanks wrote:
> > this struct and VarArgsLoweringHelper::getVarArgRegsDescriptor seem unnecessary and are only used in the is64Bit() part, can all the variables be inlined?
> @aeubanks Thank you, for the comment and Excuse me for a delayed answer. I missed a notification about that comment. This structure is used as a parameter for createVarArgAreaAndStoreRegisters() and later I am going to use it in forwardMustTailParameters(for D69372). If it would be inlined then both of these functions - createVarArgAreaAndStoreRegisters and forwardMustTailParameters will have duplicated code.  So the reason of  VarArgsLoweringHelper::getVarArgRegsDescriptor is to have single register description and avoid code duplication. 
> 
> Do you think it is still better to inline  VarArgsLoweringHelper::getVarArgRegsDescriptor ?
But it looks like `VarArgRegsDescr` is only populated, and therefore only useful when `is64Bit()` is true. And the usage of `RegDescr` in `createVarArgAreaAndStoreRegisters()` seems to support that. Or do you mean you plan on extending `getVarArgRegsDescriptor()` later? Or using `VarArgRegsDescr` in non-64 bit contexts later?


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https://reviews.llvm.org/D74794