[PATCH] D79543: [RISCV] Enable 'undisturbed' semantics in instruction definitions.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:831
 // Vector Mask-Register Logical Instructions
 defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">;
 defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">;
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Shouldn't these instructions have a maskedoff field as well? As you mention undisturbed applies both to inactive elements (masked-off) and tail elements.

That is what I understand from https://riscv.github.io/documents/riscv-v-spec/#sec-mask-register-logical

> Vector mask logical instructions are always unmasked so there are no inactive elements. Mask elements past vl, the tail elements, are unchanged.


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  https://reviews.llvm.org/D79543/new/

https://reviews.llvm.org/D79543