[PATCH] D70379: [AMDGPU] Reserving VGPR for future SGPR Spill

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:347-348
 
+/// Reserve a VGPR for spilling of SGPRs
+bool SIMachineFunctionInfo::allocateReservedVGPR(MachineFunction &MF, int FI) {
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
----------------
Better name might be reserveVGPRforSGPRSpills?


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:355
+
+  LaneVGPR = TRI->findUnusedRegister(MF.getRegInfo(), &AMDGPU::VGPR_32RegClass,
+                                     MF, true);
----------------
Define and initialize LaneVGPR at the same time


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:358
+  if (LaneVGPR == AMDGPU::NoRegister) {
+    SGPRToVGPRSpills.erase(FI);
+    return false;
----------------
Don't need this? It was never added?


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp:361
+  }
+  SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, DummyFI));
+  FuncInfo->VGPRReservedForSGPRSpill = LaneVGPR;
----------------
Don't need DummyFI, can just pass None


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70379/new/

https://reviews.llvm.org/D70379