[llvm] b55009d - [X86] Add v32i16/v64i8 into the handling for 512-bit inline assembly constraints.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Tue May 5 21:42:53 PDT 2020


Author: Craig Topper
Date: 2020-05-05T21:41:31-07:00
New Revision: b55009df666a2795741040aff87a5af5a69ec339

URL: https://github.com/llvm/llvm-project/commit/b55009df666a2795741040aff87a5af5a69ec339
DIFF: https://github.com/llvm/llvm-project/commit/b55009df666a2795741040aff87a5af5a69ec339.diff

LOG: [X86] Add v32i16/v64i8 into the handling for 512-bit inline assembly constraints.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 35c6d24ff80a..e842f1e16fc3 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -48552,6 +48552,8 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
         if (Subtarget.hasAVX())
           return std::make_pair(X86::YMM0, &X86::VR256RegClass);
         break;
+      case MVT::v64i8:
+      case MVT::v32i16:
       case MVT::v8f64:
       case MVT::v16f32:
       case MVT::v16i32:


        


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