[PATCH] D79288: [AMDGPU][MC] Enabled 21-bit signed offsets for SMEM instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM with assert nit



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Comment at: llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp:370
+  // VI only supports 20-bit unsigned offsets.
+  assert(!AMDGPU::isVI(STI) || (Offset & ~0xFFFFF) == 0);
+  return Offset;
----------------
isUINt<20> would be clearer


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79288/new/

https://reviews.llvm.org/D79288