[PATCH] D56387: [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 262099.
RKSimon retitled this revision from "[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (WIP)" to "[DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE".
RKSimon edited the summary of this revision.
RKSimon added a comment.

Add support for ANY_EXTEND ops to ARM's LowerMUL.

This fixes the main MULL regression but I'm not sure how to fix the ADDW regression which seems to be a purely isel pattern - @t.p.northover @efriedma @huihuiz any thoughts?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56387/new/

https://reviews.llvm.org/D56387

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
  llvm/test/CodeGen/ARM/lowerMUL-newload.ll
  llvm/test/CodeGen/X86/avg.ll
  llvm/test/CodeGen/X86/combine-sra.ll
  llvm/test/CodeGen/X86/known-signbits-vector.ll
  llvm/test/CodeGen/X86/min-legal-vector-width.ll
  llvm/test/CodeGen/X86/vector-trunc.ll

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