[PATCH] D79288: [AMDGPU][MC] Enabled 21-bit signed offsets for SMEM instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:3427-3441
+  uint64_t Offset = Op.getImm();
+  if (isVI() || AMDGPU::getSMEMIsBuffer(Opcode)) {
+    if (!isUInt<20>(Offset)) {
+      Error(getSMEMOffsetLoc(Operands),
+        "expected a 20-bit unsigned offset");
+      return false;
+    }
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I think we're missing the same checks in the MachineVerifier. Can you avoid spreading the hardcoded number of bits to multiple places?


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Comment at: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp:153
+  uint16_t Opcode;
+  bool is_buffer;
+};
----------------
IsBuffer


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79288/new/

https://reviews.llvm.org/D79288