[PATCH] D77202: [Target][ARM] Fold or(A, B) more aggressively for I1 Vectors
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 4 05:18:21 PDT 2020
dmgreen added a comment.
Nice. One last round of me nitpicking details I think.
What happened to the test changes in mve-pred-or.ll?
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12655
+ if (N->getOpcode() == ARMISD::VCMP)
+ Const = cast<const ConstantSDNode>(N->getOperand(2));
+ else if (N->getOpcode() == ARMISD::VCMPZ)
----------------
This can just be `return (ARMCC::CondCodes)N->getConstantOperandVal(2)`
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12667
+ return isValidMVECond(CC,
+ N->getOperand(0)->getValueType(0).isFloatingPoint());
+}
----------------
N->getOperand(0).getValueType(),...
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12690
- if (!isValidMVECond(Opposite0,
- N0->getOperand(0)->getValueType(0).isFloatingPoint()) ||
- !isValidMVECond(Opposite1,
- N1->getOperand(0)->getValueType(0).isFloatingPoint()))
+ if (!Transform || !HasVCMPOperand)
return SDValue();
----------------
Maybe make an IsFreelyInvertable() function/lambda. Then this will just be
if (IsFreelyInvertable(N0) || IsFreelyInvertable(N1))
We can then add things like swapping operands to it, if we teach it those tricks.
================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12833
+ Ops.push_back(DCI.DAG.getConstant(CC, {N0}, MVT::i32));
+ return DCI.DAG.getNode(N0->getOpcode(), {N0}, N0->getValueType(0), Ops);
+ }
----------------
Just create a SDLoc for N0. Same above in the other function.
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https://reviews.llvm.org/D77202/new/
https://reviews.llvm.org/D77202
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