[llvm] 7c649b5 - [InstCombine] Duplicate some InstSimplify tests (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Sun May 3 03:49:47 PDT 2020
Author: Nikita Popov
Date: 2020-05-03T12:49:36+02:00
New Revision: 7c649b58f02996fc89032df20d1377f8ef76f70c
URL: https://github.com/llvm/llvm-project/commit/7c649b58f02996fc89032df20d1377f8ef76f70c
DIFF: https://github.com/llvm/llvm-project/commit/7c649b58f02996fc89032df20d1377f8ef76f70c.diff
LOG: [InstCombine] Duplicate some InstSimplify tests (NFC)
Duplicate some tests in preparation for D79294.
Added:
Modified:
llvm/test/Transforms/InstCombine/assume.ll
llvm/test/Transforms/InstCombine/lshr.ll
llvm/test/Transforms/InstCombine/or-xor.ll
llvm/test/Transforms/InstCombine/shift-shift.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/assume.ll b/llvm/test/Transforms/InstCombine/assume.ll
index 66d58485a794..6f33e83ee336 100644
--- a/llvm/test/Transforms/InstCombine/assume.ll
+++ b/llvm/test/Transforms/InstCombine/assume.ll
@@ -525,6 +525,69 @@ not_taken:
ret i1 %control
}
+
+define void @always_true_assumption() {
+; CHECK-LABEL: @always_true_assumption(
+; CHECK-NEXT: ret void
+;
+ call void @llvm.assume(i1 true)
+ ret void
+
+}
+
+; The alloca guarantees that the low bits of %a are zero because of alignment.
+; The assume says the opposite. Make sure we don't crash.
+
+define i64 @PR31809() {
+; CHECK-LABEL: @PR31809(
+; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[T1:%.*]] = ptrtoint i32* [[A]] to i64
+; CHECK-NEXT: call void @llvm.assume(i1 false)
+; CHECK-NEXT: ret i64 [[T1]]
+;
+ %a = alloca i32
+ %t1 = ptrtoint i32* %a to i64
+ %cond = icmp eq i64 %t1, 3
+ call void @llvm.assume(i1 %cond)
+ ret i64 %t1
+}
+
+; Similar to above: there's no way to know which assumption is truthful,
+; so just don't crash.
+
+define i8 @conflicting_assumptions(i8 %x){
+; CHECK-LABEL: @conflicting_assumptions(
+; CHECK-NEXT: call void @llvm.assume(i1 false)
+; CHECK-NEXT: [[COND2:%.*]] = icmp eq i8 [[X:%.*]], 4
+; CHECK-NEXT: call void @llvm.assume(i1 [[COND2]])
+; CHECK-NEXT: ret i8 5
+;
+ %add = add i8 %x, 1
+ %cond1 = icmp eq i8 %x, 3
+ call void @llvm.assume(i1 %cond1)
+ %cond2 = icmp eq i8 %x, 4
+ call void @llvm.assume(i1 %cond2)
+ ret i8 %add
+}
+
+; Another case of conflicting assumptions. This would crash because we'd
+; try to set more known bits than existed in the known bits struct.
+
+define void @PR36270(i32 %b) {
+; CHECK-LABEL: @PR36270(
+; CHECK-NEXT: tail call void @llvm.assume(i1 false)
+; CHECK-NEXT: unreachable
+;
+ %B7 = xor i32 -1, 2147483647
+ %and1 = and i32 %b, 3
+ %B12 = lshr i32 %B7, %and1
+ %C1 = icmp ult i32 %and1, %B12
+ tail call void @llvm.assume(i1 %C1)
+ %cmp2 = icmp eq i32 0, %B12
+ tail call void @llvm.assume(i1 %cmp2)
+ unreachable
+}
+
declare void @llvm.dbg.value(metadata, metadata, metadata)
!llvm.dbg.cu = !{!0}
diff --git a/llvm/test/Transforms/InstCombine/lshr.ll b/llvm/test/Transforms/InstCombine/lshr.ll
index 8ab3ca887418..429a826c7981 100644
--- a/llvm/test/Transforms/InstCombine/lshr.ll
+++ b/llvm/test/Transforms/InstCombine/lshr.ll
@@ -12,7 +12,7 @@ declare <2 x i8> @llvm.ctpop.v2i8(<2 x i8>) nounwind readnone
define i32 @lshr_ctlz_zero_is_not_undef(i32 %x) {
; CHECK-LABEL: @lshr_ctlz_zero_is_not_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, 0
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: [[SH:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[SH]]
;
@@ -23,7 +23,7 @@ define i32 @lshr_ctlz_zero_is_not_undef(i32 %x) {
define i32 @lshr_cttz_zero_is_not_undef(i32 %x) {
; CHECK-LABEL: @lshr_cttz_zero_is_not_undef(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, 0
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: [[SH:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[SH]]
;
@@ -34,7 +34,7 @@ define i32 @lshr_cttz_zero_is_not_undef(i32 %x) {
define i32 @lshr_ctpop(i32 %x) {
; CHECK-LABEL: @lshr_ctpop(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, -1
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[X:%.*]], -1
; CHECK-NEXT: [[SH:%.*]] = zext i1 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[SH]]
;
@@ -45,7 +45,7 @@ define i32 @lshr_ctpop(i32 %x) {
define <2 x i8> @lshr_ctlz_zero_is_not_undef_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @lshr_ctlz_zero_is_not_undef_splat_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
; CHECK-NEXT: [[SH:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[SH]]
;
@@ -56,7 +56,7 @@ define <2 x i8> @lshr_ctlz_zero_is_not_undef_splat_vec(<2 x i8> %x) {
define <2 x i8> @lshr_cttz_zero_is_not_undef_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @lshr_cttz_zero_is_not_undef_splat_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], zeroinitializer
; CHECK-NEXT: [[SH:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[SH]]
;
@@ -67,7 +67,7 @@ define <2 x i8> @lshr_cttz_zero_is_not_undef_splat_vec(<2 x i8> %x) {
define <2 x i8> @lshr_ctpop_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @lshr_ctpop_splat_vec(
-; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, <i8 -1, i8 -1>
+; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X:%.*]], <i8 -1, i8 -1>
; CHECK-NEXT: [[SH:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[SH]]
;
@@ -76,9 +76,66 @@ define <2 x i8> @lshr_ctpop_splat_vec(<2 x i8> %x) {
ret <2 x i8> %sh
}
+define i32 @lshr_ctlz_zero_is_undef(i32 %x) {
+; CHECK-LABEL: @lshr_ctlz_zero_is_undef(
+; CHECK-NEXT: ret i32 0
+;
+ %ct = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
+ %sh = lshr i32 %ct, 5
+ ret i32 %sh
+}
+
+define i32 @lshr_cttz_zero_is_undef(i32 %x) {
+; CHECK-LABEL: @lshr_cttz_zero_is_undef(
+; CHECK-NEXT: ret i32 0
+;
+ %ct = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+ %sh = lshr i32 %ct, 5
+ ret i32 %sh
+}
+
+define <2 x i8> @lshr_ctlz_zero_is_undef_splat_vec(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_ctlz_zero_is_undef_splat_vec(
+; CHECK-NEXT: ret <2 x i8> zeroinitializer
+;
+ %ct = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %x, i1 true)
+ %sh = lshr <2 x i8> %ct, <i8 3, i8 3>
+ ret <2 x i8> %sh
+}
+
+define i8 @lshr_ctlz_zero_is_undef_vec(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_ctlz_zero_is_undef_vec(
+; CHECK-NEXT: ret i8 0
+;
+ %ct = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> %x, i1 true)
+ %sh = lshr <2 x i8> %ct, <i8 3, i8 0>
+ %ex = extractelement <2 x i8> %sh, i32 0
+ ret i8 %ex
+}
+
+define <2 x i8> @lshr_cttz_zero_is_undef_splat_vec(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_cttz_zero_is_undef_splat_vec(
+; CHECK-NEXT: ret <2 x i8> zeroinitializer
+;
+ %ct = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 true)
+ %sh = lshr <2 x i8> %ct, <i8 3, i8 3>
+ ret <2 x i8> %sh
+}
+
+define i8 @lshr_cttz_zero_is_undef_vec(<2 x i8> %x) {
+; CHECK-LABEL: @lshr_cttz_zero_is_undef_vec(
+; CHECK-NEXT: ret i8 0
+;
+ %ct = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 true)
+ %sh = lshr <2 x i8> %ct, <i8 3, i8 0>
+ %ex = extractelement <2 x i8> %sh, i32 0
+ ret i8 %ex
+}
+
+
define i8 @lshr_exact(i8 %x) {
; CHECK-LABEL: @lshr_exact(
-; CHECK-NEXT: [[SHL:%.*]] = shl i8 %x, 2
+; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], 2
; CHECK-NEXT: [[ADD:%.*]] = add i8 [[SHL]], 4
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact i8 [[ADD]], 2
; CHECK-NEXT: ret i8 [[LSHR]]
@@ -91,7 +148,7 @@ define i8 @lshr_exact(i8 %x) {
define <2 x i8> @lshr_exact_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @lshr_exact_splat_vec(
-; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> %x, <i8 2, i8 2>
+; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[X:%.*]], <i8 2, i8 2>
; CHECK-NEXT: [[ADD:%.*]] = add <2 x i8> [[SHL]], <i8 4, i8 4>
; CHECK-NEXT: [[LSHR:%.*]] = lshr exact <2 x i8> [[ADD]], <i8 2, i8 2>
; CHECK-NEXT: ret <2 x i8> [[LSHR]]
@@ -104,7 +161,7 @@ define <2 x i8> @lshr_exact_splat_vec(<2 x i8> %x) {
define i16 @bool_zext(i1 %x) {
; CHECK-LABEL: @bool_zext(
-; CHECK-NEXT: [[HIBIT:%.*]] = zext i1 %x to i16
+; CHECK-NEXT: [[HIBIT:%.*]] = zext i1 [[X:%.*]] to i16
; CHECK-NEXT: ret i16 [[HIBIT]]
;
%sext = sext i1 %x to i16
@@ -114,7 +171,7 @@ define i16 @bool_zext(i1 %x) {
define <2 x i8> @bool_zext_splat(<2 x i1> %x) {
; CHECK-LABEL: @bool_zext_splat(
-; CHECK-NEXT: [[HIBIT:%.*]] = zext <2 x i1> %x to <2 x i8>
+; CHECK-NEXT: [[HIBIT:%.*]] = zext <2 x i1> [[X:%.*]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[HIBIT]]
;
%sext = sext <2 x i1> %x to <2 x i8>
@@ -124,7 +181,7 @@ define <2 x i8> @bool_zext_splat(<2 x i1> %x) {
define i32 @smear_sign_and_widen(i8 %x) {
; CHECK-LABEL: @smear_sign_and_widen(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 7
+; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 [[X:%.*]], 7
; CHECK-NEXT: [[HIBIT:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: ret i32 [[HIBIT]]
;
@@ -135,7 +192,7 @@ define i32 @smear_sign_and_widen(i8 %x) {
define i16 @smear_sign_and_widen_should_not_change_type(i4 %x) {
; CHECK-LABEL: @smear_sign_and_widen_should_not_change_type(
-; CHECK-NEXT: [[SEXT:%.*]] = sext i4 %x to i16
+; CHECK-NEXT: [[SEXT:%.*]] = sext i4 [[X:%.*]] to i16
; CHECK-NEXT: [[HIBIT:%.*]] = lshr i16 [[SEXT]], 12
; CHECK-NEXT: ret i16 [[HIBIT]]
;
@@ -146,7 +203,7 @@ define i16 @smear_sign_and_widen_should_not_change_type(i4 %x) {
define <2 x i8> @smear_sign_and_widen_splat(<2 x i6> %x) {
; CHECK-LABEL: @smear_sign_and_widen_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i6> %x, <i6 2, i6 2>
+; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i6> [[X:%.*]], <i6 2, i6 2>
; CHECK-NEXT: [[HIBIT:%.*]] = zext <2 x i6> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[HIBIT]]
;
@@ -157,7 +214,7 @@ define <2 x i8> @smear_sign_and_widen_splat(<2 x i6> %x) {
define i18 @fake_sext(i3 %x) {
; CHECK-LABEL: @fake_sext(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr i3 %x, 2
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i3 [[X:%.*]], 2
; CHECK-NEXT: [[SH:%.*]] = zext i3 [[TMP1]] to i18
; CHECK-NEXT: ret i18 [[SH]]
;
@@ -170,7 +227,7 @@ define i18 @fake_sext(i3 %x) {
define i32 @fake_sext_but_should_not_change_type(i3 %x) {
; CHECK-LABEL: @fake_sext_but_should_not_change_type(
-; CHECK-NEXT: [[SEXT:%.*]] = sext i3 %x to i32
+; CHECK-NEXT: [[SEXT:%.*]] = sext i3 [[X:%.*]] to i32
; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[SEXT]], 31
; CHECK-NEXT: ret i32 [[SH]]
;
@@ -181,7 +238,7 @@ define i32 @fake_sext_but_should_not_change_type(i3 %x) {
define <2 x i8> @fake_sext_splat(<2 x i3> %x) {
; CHECK-LABEL: @fake_sext_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i3> %x, <i3 2, i3 2>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i3> [[X:%.*]], <i3 2, i3 2>
; CHECK-NEXT: [[SH:%.*]] = zext <2 x i3> [[TMP1]] to <2 x i8>
; CHECK-NEXT: ret <2 x i8> [[SH]]
;
@@ -194,7 +251,7 @@ define <2 x i8> @fake_sext_splat(<2 x i3> %x) {
define <2 x i32> @narrow_lshr_constant(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @narrow_lshr_constant(
-; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> %x, <i8 3, i8 3>
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i8> [[X:%.*]], <i8 3, i8 3>
; CHECK-NEXT: [[SH:%.*]] = zext <2 x i8> [[TMP1]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[SH]]
;
diff --git a/llvm/test/Transforms/InstCombine/or-xor.ll b/llvm/test/Transforms/InstCombine/or-xor.ll
index ab5f2f8ef53b..4663d196a281 100644
--- a/llvm/test/Transforms/InstCombine/or-xor.ll
+++ b/llvm/test/Transforms/InstCombine/or-xor.ll
@@ -254,8 +254,8 @@ define i32 @test16(i32 %a, i32 %b) {
define i8 @not_or(i8 %x) {
; CHECK-LABEL: @not_or(
-; CHECK-NEXT: [[NOTX:%.*]] = or i8 [[X:%.*]], 7
-; CHECK-NEXT: [[OR:%.*]] = xor i8 [[NOTX]], -8
+; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[OR:%.*]] = xor i8 [[TMP1]], -8
; CHECK-NEXT: ret i8 [[OR]]
;
%notx = xor i8 %x, -1
@@ -265,8 +265,8 @@ define i8 @not_or(i8 %x) {
define i8 @not_or_xor(i8 %x) {
; CHECK-LABEL: @not_or_xor(
-; CHECK-NEXT: [[NOTX:%.*]] = or i8 [[X:%.*]], 7
-; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[NOTX]], -12
+; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[XOR:%.*]] = xor i8 [[TMP1]], -12
; CHECK-NEXT: ret i8 [[XOR]]
;
%notx = xor i8 %x, -1
@@ -277,8 +277,8 @@ define i8 @not_or_xor(i8 %x) {
define i8 @xor_or(i8 %x) {
; CHECK-LABEL: @xor_or(
-; CHECK-NEXT: [[XOR:%.*]] = or i8 [[X:%.*]], 7
-; CHECK-NEXT: [[OR:%.*]] = xor i8 [[XOR]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[OR:%.*]] = xor i8 [[TMP1]], 32
; CHECK-NEXT: ret i8 [[OR]]
;
%xor = xor i8 %x, 32
@@ -288,8 +288,8 @@ define i8 @xor_or(i8 %x) {
define i8 @xor_or2(i8 %x) {
; CHECK-LABEL: @xor_or2(
-; CHECK-NEXT: [[XOR:%.*]] = or i8 [[X:%.*]], 7
-; CHECK-NEXT: [[OR:%.*]] = xor i8 [[XOR]], 32
+; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[OR:%.*]] = xor i8 [[TMP1]], 32
; CHECK-NEXT: ret i8 [[OR]]
;
%xor = xor i8 %x, 33
@@ -299,8 +299,8 @@ define i8 @xor_or2(i8 %x) {
define i8 @xor_or_xor(i8 %x) {
; CHECK-LABEL: @xor_or_xor(
-; CHECK-NEXT: [[XOR1:%.*]] = or i8 [[X:%.*]], 7
-; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[XOR1]], 44
+; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 7
+; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[TMP1]], 44
; CHECK-NEXT: ret i8 [[XOR2]]
;
%xor1 = xor i8 %x, 33
@@ -311,8 +311,8 @@ define i8 @xor_or_xor(i8 %x) {
define i8 @or_xor_or(i8 %x) {
; CHECK-LABEL: @or_xor_or(
-; CHECK-NEXT: [[XOR:%.*]] = or i8 [[X:%.*]], 39
-; CHECK-NEXT: [[OR2:%.*]] = xor i8 [[XOR]], 8
+; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[X:%.*]], 39
+; CHECK-NEXT: [[OR2:%.*]] = xor i8 [[TMP1]], 8
; CHECK-NEXT: ret i8 [[OR2]]
;
%or1 = or i8 %x, 33
@@ -414,3 +414,27 @@ define i32 @test22(i32 %x, i32 %y) {
%xor = xor i32 %or1, %or2
ret i32 %xor
}
+
+; (X ^ C1) | C2 --> (X | C2) ^ (C1&~C2)
+define i8 @test23(i8 %A) {
+; CHECK-LABEL: @test23(
+; CHECK-NEXT: ret i8 -1
+;
+ %B = or i8 %A, -2
+ %C = xor i8 %B, 13
+ %D = or i8 %C, 1
+ %E = xor i8 %D, 12
+ ret i8 %E
+}
+
+define i8 @test23v(<2 x i8> %A) {
+; CHECK-LABEL: @test23v(
+; CHECK-NEXT: ret i8 -1
+;
+ %B = or <2 x i8> %A, <i8 -2, i8 0>
+ %CV = xor <2 x i8> %B, <i8 13, i8 13>
+ %C = extractelement <2 x i8> %CV, i32 0
+ %D = or i8 %C, 1
+ %E = xor i8 %D, 12
+ ret i8 %E
+}
diff --git a/llvm/test/Transforms/InstCombine/shift-shift.ll b/llvm/test/Transforms/InstCombine/shift-shift.ll
index 6aa262fd931d..b53b5124ee4f 100644
--- a/llvm/test/Transforms/InstCombine/shift-shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift-shift.ll
@@ -8,9 +8,9 @@
define void @pr12967() {
; CHECK-LABEL: @pr12967(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br label %loop
+; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br label %loop
+; CHECK-NEXT: br label [[LOOP]]
;
entry:
br label %loop
@@ -27,9 +27,9 @@ loop:
define void @pr26760() {
; CHECK-LABEL: @pr26760(
; CHECK-NEXT: entry:
-; CHECK-NEXT: br label %loop
+; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
-; CHECK-NEXT: br label %loop
+; CHECK-NEXT: br label [[LOOP]]
;
entry:
br label %loop
@@ -47,14 +47,14 @@ loop:
define i32 @pr8547(i32* %g) {
; CHECK-LABEL: @pr8547(
; CHECK-NEXT: codeRepl:
-; CHECK-NEXT: br label %for.cond
+; CHECK-NEXT: br label [[FOR_COND:%.*]]
; CHECK: for.cond:
-; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
-; CHECK-NEXT: store i32 [[STOREMERGE]], i32* %g, align 4
+; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, [[CODEREPL:%.*]] ], [ 5, [[FOR_COND]] ]
+; CHECK-NEXT: store i32 [[STOREMERGE]], i32* [[G:%.*]], align 4
; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i32 [[STOREMERGE]], 6
; CHECK-NEXT: [[CONV2:%.*]] = and i32 [[TMP0]], 64
; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[CONV2]], 0
-; CHECK-NEXT: br i1 [[TOBOOL]], label %for.cond, label %codeRepl2
+; CHECK-NEXT: br i1 [[TOBOOL]], label [[FOR_COND]], label [[CODEREPL2:%.*]]
; CHECK: codeRepl2:
; CHECK-NEXT: ret i32 [[CONV2]]
;
@@ -73,3 +73,63 @@ codeRepl2:
ret i32 %conv2
}
+; Two same direction shifts that add up to more than the bitwidth should get
+; folded to zero.
+
+define i32 @shl_shl(i32 %A) {
+; CHECK-LABEL: @shl_shl(
+; CHECK-NEXT: ret i32 0
+;
+ %B = shl i32 %A, 6
+ %C = shl i32 %B, 28
+ ret i32 %C
+}
+
+define <2 x i33> @shl_shl_splat_vec(<2 x i33> %A) {
+; CHECK-LABEL: @shl_shl_splat_vec(
+; CHECK-NEXT: ret <2 x i33> zeroinitializer
+;
+ %B = shl <2 x i33> %A, <i33 5, i33 5>
+ %C = shl <2 x i33> %B, <i33 28, i33 28>
+ ret <2 x i33> %C
+}
+
+; FIXME
+
+define <2 x i33> @shl_shl_vec(<2 x i33> %A) {
+; CHECK-LABEL: @shl_shl_vec(
+; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> [[A:%.*]], <i33 6, i33 5>
+; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 27, i33 28>
+; CHECK-NEXT: ret <2 x i33> [[C]]
+;
+ %B = shl <2 x i33> %A, <i33 6, i33 5>
+ %C = shl <2 x i33> %B, <i33 27, i33 28>
+ ret <2 x i33> %C
+}
+
+define i232 @lshr_lshr(i232 %A) {
+; CHECK-LABEL: @lshr_lshr(
+; CHECK-NEXT: ret i232 0
+;
+ %B = lshr i232 %A, 231
+ %C = lshr i232 %B, 1
+ ret i232 %C
+}
+
+define <2 x i32> @lshr_lshr_splat_vec(<2 x i32> %A) {
+; CHECK-LABEL: @lshr_lshr_splat_vec(
+; CHECK-NEXT: ret <2 x i32> zeroinitializer
+;
+ %B = lshr <2 x i32> %A, <i32 28, i32 28>
+ %C = lshr <2 x i32> %B, <i32 4, i32 4>
+ ret <2 x i32> %C
+}
+
+define <2 x i32> @lshr_lshr_vec(<2 x i32> %A) {
+; CHECK-LABEL: @lshr_lshr_vec(
+; CHECK-NEXT: ret <2 x i32> zeroinitializer
+;
+ %B = lshr <2 x i32> %A, <i32 29, i32 28>
+ %C = lshr <2 x i32> %B, <i32 4, i32 5>
+ ret <2 x i32> %C
+}
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