[PATCH] D79233: [ARM] Refactor lower to S[LR]I optimization

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks for the updates. Looks like it's picked up some new tricks since the last version.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7991
+  } else {
+    ConstantSDNode *C1nodeImm = dyn_cast<ConstantSDNode>(And.getOperand(1));
+    ConstantSDNode *C1nodeShift = dyn_cast<ConstantSDNode>(And.getOperand(2));
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Can you add a comment saying this reconstructs the immediate from the BIC


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7994
+    assert(C1nodeImm && C1nodeShift);
+    C1 = C1nodeImm->getZExtValue() << C1nodeShift->getZExtValue();
+  }
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I think if this used C1 = ~(C1nodeImm->getZExtValue() << C1nodeShift->getZExtValue()) here, then the IsAnd condition below can be removed.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79233/new/

https://reviews.llvm.org/D79233