[PATCH] D79283: [PowerPC] Add missing handling for half precision

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai marked an inline comment as done.
nemanjai added inline comments.
Herald added a subscriber: wuzish.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.h:643
       const override {
-      if (VT.getScalarSizeInBits() % 8 == 0)
+      if (VT.getVectorNumElements() != 1 && VT.getScalarSizeInBits() % 8 == 0)
         return TypeWidenVector;
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@uweigand This is missing from the SystemZ back end as well and it will cause a crash on vector-enabled subtargets with `test/CodeGen/PowerPC/handle-f16-storage-type.ll` when the legalizer tries to split an `FP_EXTEND` on a `v1i16`.

The change doesn't really belong in this patch so I thought I'd just point it out.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79283/new/

https://reviews.llvm.org/D79283