[PATCH] D79073: [AMDGPU] For PAL, make sure Scratch Buffer Descriptor do not clobber GIT pointer

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:491
       .addMemOperand(MMO);
-  } else if (ST.isMesaGfxShader(Fn) ||
-             (PreloadedScratchRsrcReg == AMDGPU::NoRegister)) {
+  } else if (ST.isMesaGfxShader(Fn) || (!PreloadedScratchRsrcReg)) {
     assert(!ST.isAmdHsaOrMesa(Fn));
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Extra parentheses 


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Comment at: llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir:1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -run-pass=prologepilog -o - %s | FileCheck %s
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Comment seems to be a lie. The label and some instructions are missing 


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Comment at: llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir:9
+
+  define amdgpu_gs void @shader(i32 inreg %mergedGroupInfo) #0 {
+    ret void
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Dead "#0"


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Comment at: llvm/test/CodeGen/AMDGPU/SRSRC-GIT-clobber-check.mir:28
+  ; CHECK:   $sgpr4 = S_MOV_B32 $sgpr8, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7
+  ; CHECK:   $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM $sgpr4_sgpr5, 0, 0, 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7 :: (dereferenceable invariant load 16, align 4, addrspace 4)
+  bb.0:
----------------
Odd that we ended up with a def and implicit def of the same register


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79073/new/

https://reviews.llvm.org/D79073